Semiconductor Memory Bitline Spacer and Fence Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become more integrated, forming multiple wiring lines and buried contacts in highly-scaled devices becomes increasingly complicated due to the reduced design rule, leading to difficulties in achieving reliable product performance.
Innovation Solution
The semiconductor memory device incorporates spacer structures, fence structures, and pad isolation films, including air or silicon oxide spacers and fence liners, to improve contact reliability and reduce parasitic capacitance by isolating bitline and contact structures effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rule is reduced to increase integration density, then more devices can be formed in each area, but forming wiring lines and buried contacts becomes increasingly complicated and difficult
Solution Approach 1:
The device structure is divided into multiple functional components: bitline structures, spacer structures, contact structures, fence structures, and pad isolation films. This segmentation allows each component to be formed and optimized independently, simplifying the overall manufacturing process while maintaining high integration density
Solution Approach 2:
The invention transitions from planar 2D structures to 3D vertically-stacked structures. Bitline structures extend in a first direction while contact structures extend in a second direction perpendicular to the first, enabling higher integration density without proportionally increasing process complexity
2Productivity
If integration density is increased, then more devices fit in each area, but product reliability becomes harder to maintain
Solution Approach 1:
Fence structures act as intermediary elements between contact structures and bitline structures. These fence structures reduce parasitic capacitance and improve signal integrity, thereby enhancing reliability while maintaining high integration density
Solution Approach 2:
Pad isolation films are introduced as thin film structures to isolate contact structures on bitline structures. These isolation films prevent unwanted electrical interactions and improve device reliability without occupying significant area, thus maintaining high integration density
3Object-affected harmful factors
If contact structures are isolated using traditional methods, then parasitic capacitance is reduced, but contact resistance increases
Solution Approach 1:
The invention applies different materials and structures to different locations: pad isolation films are applied specifically at contact regions where isolation is needed, while fence structures are positioned to reduce parasitic capacitance. This localized approach reduces parasitic capacitance without compromising contact quality or increasing contact resistance
Data Source
AI summary
A semiconductor memory device includes a substrate extending in a first direction and second direction perpendicular to the first direction, bitline structures arranged on a substrate in the first direction, the bitline structures extending in the second direction, spacer structures disposed on sidewalls of the bitline structures to extend in the second direction, the spacer structures including spacers, which are formed of air or silicon oxide, contact structures disposed between the spacer structures and arranged in the second direction; fence structures filling gaps between the contact structures and between the spacer structures, and pad isolation films isolating the contact structures on the bitline structures, the spacer structures, and the fence structures. The fence structures include first fence liners and second fence liners, which are on the first fence liners and are formed of one of air and silicon oxide, and which overlap with the spacers in the first direction.