Memory Bit Line Structure with Vertical Sidewall Etching
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Solution Overview
Problem
The existing methods for manufacturing memory components result in non-vertical side walls of bit line structures during etching, leading to over-etching and damage of the bit line conductive layer, which affects the conductivity and electrical performance of the memory.
Innovation Solution
A method involving the formation of pseudo bit line layers, a support layer, and sequential stacking of bit line conductive and insulating layers, followed by removal of the support layer to create bit line structures without etching defects, thereby avoiding over-etching and improving conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the etching depth is increased to form bit line structures, then the bit line structures can be formed deeper in the substrate, but the side walls become non-vertical and the bit line conductive layer is over-etched and damaged
Solution Approach 1:
The patent introduces a mandrel structure as an intermediary element during the etching process. This mandrel serves as a temporary support that maintains side wall verticality during deep etching, preventing the bit line conductive layer from being over-etched and damaged while allowing the required etching depth to be achieved
Solution Approach 2:
The patent performs preliminary actions by first forming the mandrel structure and applying protective coatings before conducting the deep etching process. This preliminary preparation ensures that when etching occurs, the side walls are already protected and supported, preventing non-vertical formation and over-etching of the bit line conductive layer
2Length of stationary object
If the etching depth is increased to form bit line structures, then the bit line structures can be formed deeper in the substrate, but the bit line conductive layer is over-etched and damaged
Solution Approach 1:
The mandrel structure acts as a protective intermediary during etching, preventing direct exposure of the bit line conductive layer to over-etching conditions. This intermediary protection maintains the integrity and conductivity of the bit line structures even at increased etching depths
Solution Approach 2:
The patent applies protective coatings and forms the mandrel structure beforehand to cushion and protect the bit line conductive layer from the harmful effects of deep etching. This prior cushioning prevents damage that would otherwise occur during the etching process, ensuring reliable conductivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents morphological defects and over-etching of the bit line conductive layer, enhancing the electrical performance of the memory by ensuring vertical side walls and precise etching.
Implementation Method 1
The bit line structures are formed by depositing the bit line conductive layer and the bit line insulating layer sequentially
Implementation Method 2
The bit line structures are formed by depositing the bit line conductive layer and the bit line insulating layer sequentially
Data Source
AI summary
The present disclosure provides a method for manufacturing a memory, including: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer, and forming a plurality of discrete pseudo bit line layers on the substrate; forming a support layer, the support layer filling areas between the adjacent pseudo bit line layers; removing the pseudo bit line layers to form bit line spaces between adjacent parts of the support layer; forming bit line structures, the bit line structures filling the bit line spaces, and the bit line structures including a bit line conductive layer and a bit line insulating layer sequentially stacked; and removing the support layer, and forming openings between the adjacent bit line structures.