3D Memory Bit Line Via Structure for Dense Reliable Arrays
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in improving operating reliability and integration density, particularly in three-dimensional memory cell arrays.
Innovation Solution
The semiconductor memory device incorporates a bit line array with overlapping source layers and gate stack structures, channel pillars, and conductive via structures to enhance connectivity and reduce manufacturing defects, allowing for increased integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell array is used to increase integration density, then storage capacity is improved, but manufacturing complexity and defect risk increase
Solution Approach 1:
The bit line array is divided into multiple independent bit lines extending in the first direction, with each bit line serving specific memory cells. This segmentation allows for modular manufacturing and reduces the complexity of handling the entire array as a single unit, thereby enabling high integration density while maintaining manageable manufacturing processes.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells with gate stack structures extending in the third direction. This dimensional change increases storage capacity by utilizing vertical space, while the systematic arrangement of bit lines and source layers in the first and second directions provides a scalable manufacturing approach.
2Quantity of substance
If three-dimensional memory cell array is used to increase integration density, then storage capacity is improved, but operating reliability deteriorates
Solution Approach 1:
The source layers extend in the second direction and overlap with multiple bit lines, serving as common source regions for multiple memory cell strings. This multi-functional design reduces the number of separate source regions needed, simplifies the manufacturing process, and improves reliability by reducing the number of interfaces and potential failure points while maintaining high integration density.
Solution Approach 2:
The conductive via structures are disposed in the isolation structure and coupled to corresponding bit lines, acting as intermediary connection elements. This design provides reliable electrical connection between the bit lines and the memory cell structures while maintaining proper isolation, thereby improving operating reliability in the three-dimensional configuration.
3Ease of manufacture
If conventional bit line connection structure is used, then manufacturing is simpler, but connectivity and integration density are limited
Solution Approach 1:
The conductive via structures extend in the third direction through the isolation structure to connect bit lines at different vertical levels. This three-dimensional connection approach enables higher integration density by utilizing vertical interconnections, while the via structures can be formed using standard semiconductor manufacturing processes, maintaining reasonable manufacturing simplicity.
Solution Approach 2:
The isolation structure serves dual functions: providing electrical isolation between adjacent memory cell structures and serving as the medium in which conductive via structures are formed for bit line connections. This self-service design eliminates the need for separate connection structures, simplifies manufacturing, and enables higher integration density.
Data Source
AI summary
A semiconductor memory device includes a bit line array including a plurality of bit lines extending in a first direction, a plurality of source layers extending in a second direction crossing the plurality of bit lines, a plurality of gate stack structures arranged between the bit line array and the plurality of source layers, and a conductive via structure coupled to a corresponding bit line among the plurality of bit lines.