Memory Cell Programming with Split Bit-Line Voltages
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Solution Overview
Problem
Current memory devices face inefficiencies in program operation speed due to limitations in applying program voltages uniformly across memory cells, leading to variations in programming time and reliability.
Innovation Solution
The memory device employs a peripheral circuit and control logic to perform shadow and normal program operations simultaneously, applying different program control voltages to bit lines of memory cells on the same word line, allowing for efficient programming of memory cells to multiple target states concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If uniform program voltage is applied to all memory cells on a word line, then programming simplicity is maintained, but program operation speed decreases due to variations in programming time requirements
Solution Approach 1:
The memory cell group coupled to a selected word line is divided into multiple sub-groups (first sub-group and second sub-group), allowing different program control voltages to be applied to different sub-groups simultaneously. This segmentation enables parallel programming operations with different voltage levels, improving program operation speed while managing complexity through structured division.
Solution Approach 2:
Different program control voltages are applied to different sub-groups of memory cells based on their specific programming requirements. The first sub-group receives a first program control voltage while the second sub-group receives a second program control voltage, allowing each sub-group to be programmed with the appropriate voltage level for its target state, thereby optimizing program operation speed without excessive complexity.
2Productivity
If different program control voltages are applied to different memory cell groups simultaneously, then program operation speed improves, but device complexity increases
Solution Approach 1:
The peripheral circuit is configured to generate and apply different program control voltages to different sub-groups of memory cells simultaneously. This segmentation of the control function allows the peripheral circuit to manage multiple voltage levels in an organized manner, improving program operation speed while keeping the increase in device complexity manageable through functional division.
Solution Approach 2:
The peripheral circuit is designed to perform multiple functions: generating different program control voltages, selecting appropriate sub-groups, and applying voltages simultaneously to different sub-groups. This multi-functionality allows the peripheral circuit to handle complex programming operations without requiring separate dedicated circuits for each function, thereby improving program operation speed while limiting the increase in device complexity.
3Reliability
If shadow program operation is performed on some memory cells and normal program operation on others, then programming flexibility and reliability improve, but operation complexity increases
Solution Approach 1:
Memory cells are divided into different sub-groups that can undergo different programming operations (shadow program or normal program) based on their target states. This segmentation allows the memory device to apply appropriate programming methods to different cell groups, improving programming reliability while managing operation control complexity through structured division of operations.
Solution Approach 2:
Different programming operations (shadow program or normal program) are applied to different sub-groups of memory cells based on their specific requirements. This local differentiation allows each sub-group to receive the most appropriate programming method for its target state, improving programming reliability while keeping operation control complexity manageable through localized operation selection.
Data Source
AI summary
A memory device includes: a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines; a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.