Memory Array Bitstream Ratio Control for Neural Network Initialization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing designs for generating random bit streams for neural networks lack flexibility in adjusting the ratio of bit values, leading to increased manufacturing costs and circuit size, and are unable to meet the needs of processing layers requiring different ratios of '1' and '0'.

Innovation Solution

A memory system that generates random bit streams with a configurable ratio of '1' and '0' without additional random number generating circuits, using a memory device with a memory controller that adjusts program pulse strength or bias voltages to control the ratio, allowing for different ratios to be generated for various processing layers of a neural network.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If random number generating circuits are added to generate random bit streams for each processing layer, then the neural network can be initialized properly, but the manufacturing cost and circuit size increase

Engineering Contradiction:
Improveinitialization qualityVSAvoidcircuit size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory device is designed to serve dual purposes: storing training data and generating random bit streams for neural network initialization. By utilizing the inherent randomness in memory cell read operations, the system eliminates the need for separate random number generating circuits while maintaining proper initialization capability across multiple processing layers with different bit value ratios

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory device generates random bit streams using its own operational characteristics without requiring external random number generators. The randomness emerges naturally from the memory cell read operations, allowing the system to serve its own initialization needs and reducing overall circuit complexity

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If random number generating circuits are used, then random bit streams can be generated, but the design has little flexibility in adjusting the ratio of bit values for different processing layers

Engineering Contradiction:
Improveratio configurabilityVSAvoidcircuit design flexibility
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system dynamically adjusts the ratio of bit values (e.g., proportion of '1's and '0's) in the generated random bit streams by controlling the read operation parameters of memory cells. This allows different processing layers to receive appropriately configured random bit streams with different ratios, providing high adaptability without increasing circuit complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of the memory device (such as read voltage, read current, or selection criteria) to control the statistical properties of the generated random bit streams. By adjusting these parameters, the system can generate bit streams with different ratios of '1' and '0' values to match the specific requirements of different neural network processing layers

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11573768B2Memory device and method for generating random bit stream with configurable ratio of bit values
Publication Date: 2023.02.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11573768B2 patent drawing
  • US11573768B2 patent drawing
  • US11573768B2 patent drawing

AI summary

A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.