In-Memory Bitwise MAC Pipeline for Faster Parallel Accumulation
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Solution Overview
Problem
Existing multiplier-accumulators (MACs) are inefficient and require separate units for multiplication and accumulation operations, occupying significant chip real estate and limiting processing speed.
Innovation Solution
A pipelined multiplier-accumulator unit implemented in an in-memory associative processor, where multiplication and accumulation operations are integrated within a single unit, with bit-line processors performing bitwise operations in parallel, allowing simultaneous handling of carry and sum bits across a matrix of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate MAC units are implemented in CPU or DSP, then multiplication and accumulation operations can be performed, but chip real estate is significantly occupied and processing speed is limited
Solution Approach 1:
The patent merges multiplication and accumulation operations into a single integrated MAC unit that processes multiple operations simultaneously. The MAC unit combines the multiplier, adder, and accumulator into one unified structure, eliminating the need for separate functional units and reducing chip area while improving processing throughput.
Solution Approach 2:
The patent introduces a temporal dimension through pipelining, organizing the MAC operations into multiple stages that process different data simultaneously. The pipeline structure allows multiple multiplication-accumulation operations to be in different stages of execution at the same time, increasing throughput without proportionally increasing chip area.
2Productivity
If traditional MAC architecture with separate multiplier and adder units is used, then operations are well-defined, but device complexity increases and processing efficiency decreases
Solution Approach 1:
The patent combines the multiplier, adder, and accumulator into a single integrated MAC unit. This merging reduces the number of separate components and interconnections, simplifying the overall architecture while enabling more efficient processing through unified operation control and reduced data movement overhead.
Solution Approach 2:
The MAC unit is designed as a universal computing element that can perform multiple operations (multiplication, accumulation, and their combinations) within a single structure. This multi-functionality reduces the need for specialized units for different operations, simplifying the architecture while maintaining processing efficiency.
3Speed
If sequential processing of multiplication and accumulation is implemented, then operation accuracy is maintained, but processing speed is limited
Solution Approach 1:
The patent implements a dynamic pipeline structure where data flows through multiple stages of processing simultaneously. The pipeline allows different multiplication-accumulation operations to be in different stages (fetch, execute, accumulate) at the same time, enabling parallel processing while maintaining the correctness of sequential operations through proper stage synchronization.
Solution Approach 2:
The pipeline structure performs preliminary actions in advance - multiplication results are prepared and staged before accumulation is complete, and the next multiplication operation can begin while the previous accumulation is still in progress. This preliminary preparation enables overlapping of operations, increasing throughput without compromising accuracy.
Data Source
AI summary
A unit for accumulating multiplied bit values includes an array of bit-line processors. The unit is implemented in an in-memory associative processor, and each bit-line processor includes multiple memory cells coupled to a bit-line. The array of processors is arranged in rows and columns. The array passes bits of a first multiplicand vertically down a column and provides bits of a second multiplicand horizontally across a row. The array generates carry bits and passes them vertically to a subsequent processor in the same column. The array also generates sum bits and passes them diagonally to a subsequent processor in an adjacent column. The array includes multiplying processors, summing processors, and accumulator processors. Multiplying processors perform an XOR operation by simultaneously activating two memory cells and then perform a full adder operation. Summing processors perform a full adder operation. Accumulator processors perform a full adder operation that includes a feedback sum bit from a previous cycle.