Semiconductor Memory Bitwise Encoding for Balanced Soft Error Detection
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Solution Overview
Problem
Existing methods for soft error detection in semiconductor devices, such as using test data, double RAM algorithms, and ECC functions, suffer from unbalanced detection rates for data stored as fixed values of '0s' and '1s', leading to performance degradation and implementation difficulties.
Innovation Solution
A semiconductor device with a bitwise operation unit that generates data with an equal number of '1s' and '0s' and a storage control unit that stores this data in separate destinations, using bitwise operations and bit inversion to balance detection rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If actual data is used for soft error detection using the double RAM algorithm, then detection is performed during normal operation, but the soft error detection rates for data stored as fixed '0s' and '1s' become unbalanced
Solution Approach 1:
The patent applies parameter changes by XORing the actual data with predetermined check data before storing it in the second RAM. This transformation changes the data parameters so that even if the original data has extreme values (all 0s or all 1s), the transformed data will have a more balanced distribution of 0s and 1s. During detection, the same XOR operation is performed on the read data with the stored check data, and the results are compared to detect soft errors while maintaining balanced detection rates for both 0 and 1 fixed values.
2Reliability
If test data is used for soft error detection, then detection can be performed periodically, but the probability of radioactive ray collision is low and sufficient detection rate cannot be achieved
Solution Approach 1:
The patent introduces check data as an intermediary element that assists in the soft error detection process. The check data is XORed with the actual data before storage, and the same operation is performed during read operations. This intermediary mechanism enables effective soft error detection without requiring separate test data writing and reading operations, thereby achieving both high reliability and maintained productivity during normal system operation.
3Reliability
If ECC function is used for soft error detection, then detection accuracy is improved, but it is difficult to adopt for RAM without ECC hardware and software processing load is high
Solution Approach 1:
The patent replaces the complex ECC hardware and software with a simpler, lightweight approach using basic XOR operations and standard RAM components. Instead of implementing sophisticated error correction codes that require dedicated hardware circuits and complex software algorithms, the invention uses a simple bitwise XOR operation with predetermined check data, which can be implemented with minimal hardware overhead and negligible software processing load, achieving effective soft error detection without the complexity of traditional ECC systems.
Data Source
AI summary
A semiconductor device includes a bitwise operation unit and a storage control unit. The bitwise operation unit performs a bitwise operation on first n-bit (n is an integer) data that is storage object data and second data of an n-bit bit pattern and generates third data of a bit pattern that the number of “1s” and the number of “0s” are almost the same as each other. The storage control unit stores the third data into a first storage destination of a storage unit and stores fourth data that is the third data or data that is converted into the third data by performing a bitwise operation that has been predetermined in advance on the data into a second storage destination of the storage unit.