Memory Blast-Mode Last-Cycle Detection for Faster Column Access
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Solution Overview
Problem
The speed of processing units is limited by the latency in reading and writing data to and from memory, particularly in SRAM, due to row and column changes and other operations, which contribute to higher clock cycles.
Innovation Solution
A control circuitry is introduced to detect the rising edge of a closing cycle in multi-cycle operations, enabling a 'blast mode' where multiple words are read or written across multiple columns, utilizing a state machine, registers, and a last cycle detection circuit to optimize memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sequential memory operations are used, then each word access requires a complete clock cycle, but this results in higher latency and reduced processing speed
Solution Approach 1:
The patent segments the memory access operation into multiple parallel columns, allowing multiple words to be accessed simultaneously across different columns. The state machine divides the blast operation into individual column operations, each handled by separate register and logic circuitry, enabling parallel processing that reduces overall access time while maintaining complete clock cycle integrity
Solution Approach 2:
The patent implements preliminary action through the state machine and register circuitry that pre-establish the sequence of column operations before execution. The address enable signal is pre-loaded into registers, and the state machine pre-determines the operation sequence, allowing the memory system to be ready for rapid sequential access without requiring full clock cycle completion for each individual word
2Productivity
If multiple words are accessed individually in sequential order, then each access is completed accurately, but the throughput is reduced due to multiple clock cycles required
Solution Approach 1:
The patent implements multi-functionality through a universal control circuit that handles both single-word and multi-word (blast) operations using the same state machine and register infrastructure. The control circuitry can dynamically adapt to different operation modes (read, write, blast read, blast write) without requiring separate dedicated circuits for each function, thereby increasing throughput while managing complexity through design reuse
Solution Approach 2:
The patent introduces intermediary elements including the state machine, registers, and detection circuitry that mediate between the control signals and the memory array. These intermediaries translate high-level blast operation commands into precise column-by-column execution sequences, enabling increased throughput while maintaining accurate control through layered signal processing
3Adaptability or versatility
If row and column changes are performed frequently, then memory flexibility is maintained, but latency increases due to operation overhead
Solution Approach 1:
The patent implements periodic action through the clocked state machine that systematically progresses through column operations in regular intervals. The state machine advances through predefined states corresponding to different columns, creating a periodic rhythm to the blast operation that maintains flexibility for different access patterns while reducing latency through predictable, timed transitions rather than arbitrary row/column changes
Data Source
AI summary
Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.