Memory Blast-Mode Writes to Reduce Clock-Cycle Overhead
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Solution Overview
Problem
The speed of processing units is limited by the latency in reading and writing data to memory, particularly in static random access memory (SRAM), due to the need for multiple clock cycles per word operation and the overhead of row and column changes.
Innovation Solution
Implementing a 'blast mode' write operation where multiple words are written simultaneously on a wordline across multiple columns, reducing the number of clock cycles required by pre-charging bitlines and minimizing the need for repeated wordline activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple words are written individually to memory, then each word can be written with proper timing and control, but the number of clock cycles required increases, reducing throughput and increasing latency
Solution Approach 1:
The patent merges multiple individual write operations into a single combined write operation. By loading multiple words into a buffer and triggering them simultaneously through a single wordline activation, the system performs what would traditionally require multiple separate operations in just one operation, thereby increasing throughput and reducing the number of clock cycles required.
Solution Approach 2:
The patent applies preliminary action by pre-loading multiple words into a buffer before the actual write operation. This allows the data to be prepared and staged in advance, so that when the write trigger is activated, all words are ready to be written simultaneously without requiring individual loading and timing sequences for each word.
2Ease of operation
If wordline is activated for each write operation, then precise control over when data is written is achieved, but the frequency of wordline activation increases, consuming more power and increasing latency
Solution Approach 1:
The patent combines multiple wordline activations into a single activation event. Instead of turning the wordline on and off for each individual write operation, the system loads multiple words into a buffer and then activates the wordline once to write all words simultaneously, thereby reducing power consumption while maintaining operational control.
Solution Approach 2:
The patent maintains continuity of useful action by keeping the wordline activated for the duration of the buffered write operation. Once the wordline is activated, multiple words are written in sequence or parallel without requiring the wordline to be turned off and re-activated, thereby reducing the frequency of activation events and associated power consumption.
3Reliability
If bitlines are pre-charged for each write operation, then reliable data writing is ensured, but repeated pre-charging increases power consumption and operation time
Solution Approach 1:
The patent applies preliminary action by pre-charging the bitlines in advance of the actual write operation. The bitlines are charged to the appropriate voltage levels during the buffer loading phase, so that when the write trigger is activated, the bitlines are already prepared to receive the data without requiring repeated pre-charging cycles for each word.
Data Source
AI summary
A method for write operations to memory include starting write operations for writing n words in a same row, including loading a first word of the n words during a first clock cycle, where n is an integer greater than 1; loading one or more additional words of the n words, each during a corresponding one or more additional clock cycles; triggering the n words to be stored in the memory; and closing the write operations for the writing of the n words during a final clock cycle, whereby the n words are written in n+1 clock cycles consisting of the first clock cycle, the corresponding one or more additional clock cycles, and the final clock cycle. The write circuitry performing the aforementioned operations can also perform write operations for a single word in two clock cycles.