Semiconductor Memory Block Array Segmentation for Noise-Resistant Simultaneous Access
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Solution Overview
Problem
Existing semiconductor memory devices, such as MRAM, face challenges in simultaneous access due to increased circuit noises during simultaneous reading and writing operations, and existing standards like LPDDR2 are not suitable for non-volatile memories due to complex state transitions.
Innovation Solution
A semiconductor memory device with a block array configuration, including a page selection circuit, page buffer, row selection circuit, and column selection circuit, allows for independent selection and operation of memory cells using RAS, CAS, READ, and WRITE commands, enabling simultaneous access without increasing circuit noises and simplifying state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reading and writing are simultaneously performed to a plurality of MTJ elements using current, then non-volatile and high-speed access is achieved, but circuit noises increase making simultaneous access difficult
Solution Approach 1:
The memory device is divided into multiple independent memory blocks (first memory block, second memory block, etc.), each capable of independent row and column selection. This segmentation allows simultaneous access to different memory blocks without interfering with each other, as each block has its own selection circuits and operates independently, thus enabling simultaneous access while avoiding noise interference between operations.
Solution Approach 2:
Row selection circuits and column selection circuits serve as intermediaries between the control signals and the memory cells. These selection circuits enable precise addressing and isolation of specific memory blocks, allowing simultaneous operations in different blocks while preventing noise propagation. The selection circuits act as mediators that coordinate access and prevent harmful interactions between simultaneous read and write operations.
2Loss of energy
If LPDDR2 specification is applied to non-volatile memories, then low-power consumption is achieved, but state transition complexity increases making it unsuitable for MRAM
Solution Approach 1:
Instead of adapting non-volatile memory to complex DRAM-like specifications (LPDDR2), the invention inverts the approach by designing a memory interface and control system specifically optimized for non-volatile memory characteristics. The control system manages state transitions in a manner appropriate for MRAM's inherent properties, avoiding the complex state machine requirements of LPDDR2 while maintaining low power consumption through efficient, simplified control logic tailored to non-volatile memory operations.
3Speed
If multiple memory blocks are accessed simultaneously with current-based read/write, then access speed is improved, but noise interference prevents reliable simultaneous access
Solution Approach 1:
The memory system is segmented into multiple independent memory blocks, each with dedicated row selection circuits and column selection circuits. This segmentation enables simultaneous access to multiple blocks at high speed while maintaining reliability, as each block operates independently with its own selection logic, preventing noise interference between concurrent operations in different blocks.
Solution Approach 2:
Each memory block is equipped with local row selection circuits and column selection circuits that provide precise, localized control over memory cell access. This local quality ensures that simultaneous operations in different blocks do not interfere with each other, maintaining high reliability while enabling fast parallel access across multiple blocks.
Data Source
AI summary
A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array from which a page is to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array.