Memory Block BFEA Scans for Low-Latency Power-On Classification

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional block family error avoidance (BFEA) scans at power on of memory devices are resource-intensive, leading to system performance issues and boot up latency due to insufficient idle time for correct bin classification of all blocks.

Innovation Solution

Perform a quick power on BFEA scan using a first-in-first-out (FIFO) queue to prioritize blocks based on drift time since the last scan, selecting a subset of blocks for scanning to update bin classifications, thereby reducing the number of scans needed and minimizing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional BFEA scan is performed at power on to classify all blocks into bins, then accurate bin classification is achieved, but system performance deteriorates and boot up latency increases due to resource-intensive scanning

Engineering Contradiction:
Improvebin classification accuracyVSAvoidboot up latency
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs BFEA scans on only a subset of blocks (e.g., 1-5 blocks per bin) rather than all blocks in the memory device. This partial scanning approach provides sufficient bin classification accuracy for operational purposes while dramatically reducing the time and resources required, thus resolving the contradiction between classification accuracy and boot up latency.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent maintains a scan queue that persists across power cycles, storing the state of which blocks have been scanned and their bin classifications. This preliminary action allows the system to resume scanning where it left off rather than starting over, reducing boot up latency while maintaining accurate bin classification through incremental updates.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a conventional BFEA scan is performed at power on to ensure all blocks are correctly classified, then reliability is improved, but productivity deteriorates due to insufficient idle time and resource consumption

Engineering Contradiction:
Improveblock classification reliabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent scans only a representative subset of blocks (1-5 blocks per bin) rather than all blocks, which provides sufficient reliability for determining bin characteristics while preserving system productivity. The scanned subset is statistically representative enough to ensure reliable bin classification without consuming excessive resources.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements a persistent scan queue that automatically manages which blocks need scanning and maintains classification state across power cycles. This self-service mechanism reduces the need for comprehensive rescanning at each power on, maintaining reliability while improving productivity by avoiding redundant scanning operations.

Inventive Principle:
Principle #25Self-service

3Loss of time

If a quick BFEA scan is performed on only a subset of blocks to reduce latency, then boot up time is improved, but bin classification accuracy may deteriorate

Engineering Contradiction:
Improveboot up latencyVSAvoidbin classification accuracy
Core Design Contradiction:
Loss of timeVSMeasurement precision

Solution Approach 1:

The patent maintains a persistent scan queue that stores classification state from previous scans. This preliminary action allows the system to quickly resume operations using existing classification data while performing minimal additional scans, thus reducing boot up latency while maintaining bin classification accuracy through incremental updates rather than complete rescanning.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses the results from scanning a small subset of blocks to update and refine bin classifications, with the understanding that these classifications will be further refined by subsequent scans of remaining blocks. This feedback mechanism ensures that even with partial scanning, the bin classifications remain accurate enough for operational purposes while minimizing boot up latency.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250316324A1Quick power on block family error avoidance scan
Publication Date: 2025.10.09 MICRON TECHNOLOGY INC
  • US20250316324A1 patent drawing
  • US20250316324A1 patent drawing
  • US20250316324A1 patent drawing

AI summary

A scan pool comprising a set of blocks of a memory device is generated. Each block in the set of blocks is classified into one of multiple predefined bins and each bin of the multiple bins have a corresponding set of read level voltage offsets. Scan targets for a first bin of the multiple predefined bins are determined based on the scan pool. The scan targets include a first block, a second block, and a third block from a subset of blocks from the set of blocks that are classified into the first bin. Block family error avoidance (BFEA) scans are performed on only the scan targets. Bin classifications for other blocks in the subset of blocks are updated based on a result of the BFEA scans on only the scan targets.