Memory Block Error Correction via Check Code Segmentation

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Solution Overview

Problem

In-memory search systems face reliability issues due to error bits in stored data, which affect the accuracy of search results.

Innovation Solution

A memory device with error correction capabilities, comprising memory blocks, driving circuits, an error correction circuit, and a control circuit, where each memory block includes data columns and check columns, allowing for error detection and correction using check codes generated for user data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction operation is performed on stored data, then reliability of search results is improved, but operation time and complexity increase

Engineering Contradiction:

Improvereliability of search resultsVSAvoidoperation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing check codes alongside user data in the memory blocks. This allows the error correction circuit to perform rapid error detection and correction during search operations by simply comparing the stored check codes with newly generated ones, rather than performing complex error correction calculations in real-time, thus improving reliability while minimizing time loss.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If check columns are added to memory blocks, then error detection capability is improved, but device complexity increases

Engineering Contradiction:

Improveerror detection capabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the memory block into distinct data columns and check columns. Each column is independently managed with dedicated driving circuits, allowing the error correction functionality to be added without fundamentally redesigning the entire memory structure. This modular approach improves error detection capability while controlling device complexity through structured organization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements universality by designing the memory block structure to serve multiple functions: data storage in data columns and error correction in check columns. The same memory block infrastructure supports both normal data operations and error correction operations, eliminating the need for separate error correction hardware and reducing overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Measurement precision

If error correction circuit is integrated, then data accuracy is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvedata accuracyVSAvoidmanufacturing complexity

Core Design Contradiction:

Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent applies merging by integrating the error correction circuit with the existing memory block structure and driving circuits. The error correction functionality is combined with the data readout path, allowing both data retrieval and error correction to be performed through the same circuitry. This integration improves data accuracy while simplifying manufacturing by reducing the number of separate components and interconnections required.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11847021B2Memory block, memory device for error correction operation and method thereof

Publication Date: 2023.12.19 MACRONIX INTERNATIONAL CO LTD

AI summary

An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.