Semiconductor Memory Block Decoder Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices require multiple block decoders for each memory cell block, leading to increased area occupation and reduced integration levels, especially in high-capacity flash memory devices.
Innovation Solution
A semiconductor memory device design where a single block decoder controls two memory cell blocks, utilizing a control signal generator, precharge units, and enable units to generate and manage block select signals, reducing the need for multiple decoders and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple block decoders are used for each memory cell block, then each block can be controlled independently, but the area occupied by block decoders increases and integration level decreases
Solution Approach 1:
A single block decoder is designed to control multiple memory cell blocks (first and second blocks) through shared control signals. The block decoder generates block select signals that can independently select different blocks, allowing one decoder to perform the function of multiple decoders would have performed, thereby reducing the total area occupied by decoder circuits while maintaining independent block control capability
Solution Approach 2:
The patent combines multiple block decoder functions into a single integrated block decoder unit. By merging the control logic and signal generation capabilities for multiple blocks into one decoder, the design eliminates redundant decoder circuits and reduces the overall area occupied by block decoders in the memory device
2Ease of operation
If multiple block decoders are used for each memory cell block, then block control is simplified, but device complexity increases
Solution Approach 1:
The block decoder is designed as a universal control unit that can select and control any of the multiple memory cell blocks through shared control signals. This multi-functional design simplifies the overall device complexity by replacing multiple specialized decoders with one versatile decoder that handles all block selection tasks
3Area of stationary object
If a single block decoder controls two memory cell blocks, then area occupation is reduced and integration level is improved, but control signal management becomes more complex
Solution Approach 1:
The block decoder internally segments control signals for different memory blocks through separate control signal lines (first block select signal and second block select signal). This segmentation allows the single decoder to manage multiple blocks independently by generating distinct control signals for each block, simplifying the management of control signals while maintaining area efficiency
Data Source
AI summary
A semiconductor memory device includes first and second memory cell blocks, a block decoder, and first and second block switches. The first and second memory cell blocks have a plurality of memory cells connected in a string structure and are respectively disposed in neighboring planes. The block decoder outputs first and second block select signals in response to pre-decoded address signals and first and second plane select signals, which are respectively enabled according to an enable state of the planes. The first and second block switches connect global word lines to word lines of the first and second memory cell blocks in response to the first and second block select signals, respectively.