Semiconductor Memory Block Discharge Voltage Control
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Solution Overview
Problem
In semiconductor memory devices with shared row decoders, the gate-induced-drain-leakage phenomenon during read operations leads to an increase in the threshold voltage distribution of unselected memory blocks, affecting their performance.
Innovation Solution
Applying a discharge voltage to the unselected memory block after the read voltage is terminated in the selected memory block, using a semiconductor memory device with a peripheral circuit that generates and applies specific voltages to manage this process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a read operation is performed on a selected memory block in a semiconductor memory device with shared row decoders, then data can be read from the selected block, but electron-hole pairs are generated due to gate-induced-drain-leakage in unselected memory blocks causing threshold voltage distribution to widen
Solution Approach 1:
The patent applies preliminary anti-action by discharging the unselected memory block before the gate-induced-drain-leakage effect can cause significant threshold voltage shift. The discharge operation is performed in advance during the read operation of the selected block, counteracting the harmful EHP generation effect before it can degrade reliability.
Solution Approach 2:
The patent converts the harmful gate-induced-drain-leakage effect into a beneficial discharge opportunity. By applying a discharge voltage to the unselected memory block during the read operation, the harmful EHP generation is transformed into a controlled discharge process that actually improves threshold voltage stability.
2Device complexity
If multiple memory blocks share a single row decoder to reduce device complexity, then the device structure is simplified, but gate-induced-drain-leakage occurs between bit line and drain selection transistor in unselected blocks during read operations
Solution Approach 1:
The patent applies local quality by treating the selected and unselected memory blocks differently during read operations. The selected block receives read voltage for data access, while the unselected block receives discharge voltage to prevent harmful effects. This localized differential treatment allows shared row decoder structure to remain simple while eliminating the harmful leakage effect.
3Reliability
If discharge voltage is applied to unselected memory block during read operation, then threshold voltage distribution is maintained stable, but additional voltage control complexity is introduced
Solution Approach 1:
The patent merges the discharge function with the existing row decoder voltage control mechanism. The same row decoder that selects memory blocks also controls the discharge voltage application to unselected blocks, combining multiple functions into a single control path and avoiding additional voltage control complexity.
Solution Approach 2:
The row decoder is given multi-functionality, serving both as the selection control for read operations and as the discharge control for unselected blocks. This universal approach allows a single control circuit to handle multiple functions, reducing overall device complexity while maintaining threshold voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the increase in channel potential of unselected memory blocks, maintaining a stable threshold voltage distribution and improving the overall performance of the semiconductor memory device.
Implementation Method 1
electron-hole pairs (EHP) may be generated due to a gate-induced-drain-leakage (GIDL) phenomenon between a bit line and a drain selection transistor and between a source line and a source selection transistor
Data Source
AI summary
The present invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device may include at least two memory blocks sharing a row decoder, and a peripheral circuit performing a read operation on a selected memory block, between the at least two memory blocks, wherein the peripheral circuit applies a discharge voltage to an unselected memory block, between the at least two memory blocks, for a preset time after a period in which a read voltage is applied to the selected memory block is terminated.