Semiconductor Memory Block Layout for Independent Erase Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing data erasure across memory blocks, leading to reduced service life and decreased integration density due to increased garbage collection operations.
Innovation Solution
The semiconductor memory device is configured to independently erase data in separate memory blocks, allowing for different voltage applications to select gate lines, which stabilizes the erase operation and reduces the number of garbage collection executions, thereby extending service life while maintaining integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data erasure is performed across memory blocks using conventional methods, then integration density can be increased, but service life is reduced due to increased garbage collection operations
Solution Approach 1:
The memory device is divided into multiple independently erasable memory blocks (first memory block and second memory block). Each block can be erased separately by applying different voltages to their respective select gate lines, allowing selective garbage collection without affecting other blocks. This segmentation reduces the frequency of full memory erasure operations, thereby extending service life while maintaining high integration density.
2Reliability
If independent erase operations are implemented for separate memory blocks, then service life is extended by reducing garbage collection operations, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple independently erasable memory blocks (first memory block and second memory block). Each block can be erased separately by applying different voltages to their respective select gate lines, allowing selective garbage collection without affecting other blocks. This segmentation reduces the frequency of full memory erasure operations, thereby extending service life while maintaining high integration density.
Solution Approach 2:
Different voltage levels are applied to different select gate lines (first select gate line and second select gate line) to enable independent erase operations in different memory blocks. This local differentiation allows targeted garbage collection in specific blocks that need it, rather than erasing the entire memory device, thus extending service life without proportionally increasing complexity.
Data Source
AI summary
A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.