Memory Block Erase-Verify Skipping for Faster EOL Cycling
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Solution Overview
Problem
Existing memory devices, particularly NAND memory devices, face challenges in improving the speed of End of Life (EOL) cycling and testing processes due to the time-consuming nature of erase verify operations, which can be optimized for faster performance.
Innovation Solution
An erase scheme is introduced that skips the erase verify step during program and erase cycles, allowing for a pre-programming and erase pulse to be applied to memory cells while omitting the erase verify operation, with the option to resume verify operations after reaching a threshold number of cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase verify operation is performed for all memory cells during EOL cycling, then data integrity and reliability are ensured, but cycling speed and productivity are reduced
Solution Approach 1:
The patent applies partial action by performing erase verify operations only on a subset of memory cells (e.g., first portion of blocks) rather than all cells. This selective verification maintains sufficient reliability for data integrity while significantly improving cycling speed by skipping verify operations on remaining cells during EOL testing.
Solution Approach 2:
The patent implements the skipping principle by omitting the erase verify step entirely for certain memory cells or blocks during EOL cycling. This allows the testing process to rush through the verification phase, achieving faster cycling speeds while relying on alternative verification methods or accepting reduced verification coverage for non-critical cells.
2Productivity
If erase verify step is skipped to reduce block erase time, then productivity and cycling speed are improved, but measurement precision and reliability of erase operation are reduced
Solution Approach 1:
The patent employs feedback mechanisms where the controller monitors erase operation results and adjusts subsequent operations accordingly. Even when verify steps are skipped, the system uses feedback from partial verifications, error detection, and retry logic to ensure erase operations achieve the required precision and reliability thresholds.
Solution Approach 2:
The patent changes operational parameters such as voltage levels, pulse durations, and verification thresholds to optimize the balance between erase speed and verification accuracy. By adjusting these parameters, the system achieves faster block erase times while maintaining sufficient measurement precision through optimized verification protocols.
3Reliability
If full erase verify operation is performed on all blocks, then data reliability is maintained, but time consumption and processing duration increase
Solution Approach 1:
The patent segments the memory array into multiple portions or blocks and applies different verification strategies to each segment. Critical data regions undergo full verification while less critical regions undergo reduced verification, thereby maintaining overall data reliability while significantly reducing total testing duration through parallel processing of different segments.
Solution Approach 2:
The patent implements dynamic verification strategies where the controller adapts the verification intensity based on real-time conditions, error rates, and data criticality. This dynamic approach allows the system to allocate more verification resources to high-risk areas while reducing verification effort in stable regions, optimizing the balance between reliability and testing time.
Data Source
AI summary
Methods, systems, and devices for erase verify skip for fast cycling are described. A memory device may receive a command to perform an erase operation involving a first type of erase operation excluding an erase verify operation, and may apply a pre-programming pulse and an erase pulse to a block of memory cells while skipping an erase verify operation for one or more memory cells of the block based on the command. In some examples, the memory device may skip one or more erase verify operations based one or more internal trim settings. Additionally, or alternatively, erase verify skipping may be adaptive. For example, once a quantity of erase operations satisfies a threshold quantity, the memory device may receive a second command and may perform a second erase operation involving performing an erase verify operation for one or more memory cells of the block.