Memory Block Erasure Using Segmented Word Line Activation
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Solution Overview
Problem
Current memory block erasure methods in computer systems are inefficient due to high complexity and latency, especially when clearing large blocks of memory, as they require activating a single word line at a time, leading to many processor cycles and increased energy consumption.
Innovation Solution
Implementing a divide and conquer approach by initially erasing a few cells on a bit line, activating them in subsequent iterations to reduce hysteresis, and using a binary power series to double the number of activated cells, with word lines distributed to minimize resistance and reduce energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single word line is activated at a time for memory block erasure, then the erasure process is simple to implement, but the time required and energy consumption increase significantly
Solution Approach 1:
The memory block erasure process is segmented into multiple iterations, where each iteration activates a subset of word lines (initially one, then progressively more) rather than all word lines simultaneously. This segmentation allows the system to balance between implementation simplicity and erasure efficiency, reducing total erasure time while maintaining manageable complexity through controlled progression of activated word lines.
Solution Approach 2:
The erasure process employs periodic action through multiple iterations, where word lines are activated in periodic cycles. Each iteration activates additional word lines based on a binary power series pattern, creating a rhythmic progression that systematically reduces the number of inactive word lines over time, thereby reducing total erasure time while maintaining systematic control.
2Device complexity
If a single word line is activated at a time for memory block erasure, then the control logic is simple, but energy consumption increases due to more processor cycles
Solution Approach 1:
The control logic is segmented to manage word line activation in controlled iterations rather than all at once. By dividing the erasure process into stages where subsets of word lines are activated progressively, the control logic maintains reasonable complexity while significantly reducing the total number of processor cycles required, thereby lowering energy consumption.
Solution Approach 2:
The system performs preliminary actions by activating initial word lines in each iteration before proceeding to the next set. This preliminary activation of specific word lines (following a binary power series pattern) prepares the memory block for subsequent erasure operations, reducing the total number of cycles needed and thus reducing overall energy consumption while keeping control logic manageable.
3Loss of time
If all word lines are activated simultaneously for memory block erasure, then the erasure time is minimized, but the resistance and energy consumption increase
Solution Approach 1:
Instead of activating all word lines simultaneously, the process segments activation into multiple iterations with progressively increasing subsets of word lines. This segmentation finds an optimal balance between erasure time and energy consumption by activating word lines in controlled groups rather than all at once, reducing peak resistance and overall energy usage while maintaining efficient erasure speed.
Solution Approach 2:
The system dynamically adjusts the number of activated word lines across iterations, following a binary power series progression. This dynamic approach allows the system to optimize the balance between erasure speed and energy consumption by adaptively increasing activation levels, thereby minimizing resistance effects and energy usage while achieving fast erasure times.
4Productivity
If multiple word lines are activated simultaneously, then the erasure speed increases, but the hysteresis effect becomes more significant
Solution Approach 1:
The activation process is segmented into iterations where word lines are activated in progressively larger subsets rather than all simultaneously. This segmentation controls the hysteresis effect by limiting the number of active word lines at any given time, while still achieving high erasure speed through the cumulative effect of multiple iterations following a binary power series pattern.
Solution Approach 2:
The system uses periodic action through multiple iterations to manage hysteresis while maintaining high erasure speed. Each iteration periodically activates additional word lines in a controlled manner, allowing the system to achieve fast erasure overall while managing peak hysteresis effects through rhythmic, staged activation rather than simultaneous activation of all word lines.
Data Source
AI summary
Embodiments of memory block erasure are described herein. An aspect includes determining an initial word line set consisting of a single word line. Another aspect includes activating the single word line such that a first memory cell that is connected to the single word line is erased by the activation. Another aspect includes determining a first word line set consisting of the single word line and one additional word line, and wherein the one additional word line corresponds to a second memory cell have a maximum distance from the first memory cell along a bit line that includes the first memory cell and the second memory cell. Another aspect includes activating the first word line set, such that a respective memory cell that is connected to each of the first word line set is erased by the activation.