Memory Subsystem Block Family Calibration for Voltage Shift
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Solution Overview
Problem
Existing memory sub-systems face increased bit error rates due to temporal voltage shift caused by slow charge loss in memory cells, which is not adequately addressed by current technologies, leading to inefficient strategies and high error rates.
Innovation Solution
Implementing a memory sub-system that tracks temporal voltage shift for programmed memory cells grouped by block families and applies appropriate voltage offsets to base read levels for read operations, using a block family manager to periodically calibrate threshold voltage offset bins and reduce read bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage offsets are applied to compensate for temporal voltage shift, then read bit error rate is reduced, but device complexity increases due to calibration operations
Solution Approach 1:
The patent segments memory blocks into block families based on their programming characteristics and temporal voltage shift behavior. By grouping blocks with similar characteristics together, the system can apply calibration operations to representative blocks only, rather than every individual block, thus reducing complexity while maintaining reliability.
Solution Approach 2:
The patent performs preliminary calibration operations during manufacturing or initial programming to establish baseline threshold voltage offset bins. These pre-established bins are then used as reference for ongoing operations, reducing the need for frequent full calibrations and lowering operational complexity.
2Measurement precision
If calibration operations are performed frequently to maintain accuracy, then threshold voltage offset precision is improved, but processing resources are consumed
Solution Approach 1:
The patent implements periodic calibration operations at predetermined intervals or under specific conditions (e.g., after a certain number of programming cycles or time periods). This approach maintains threshold voltage offset precision by recalibrating only when necessary, rather than continuously, thus preserving processing resources.
Solution Approach 2:
The system monitors its own operational state and automatically triggers calibration operations when performance degradation is detected. This self-service mechanism ensures precision is maintained while avoiding unnecessary calibrations that would consume processing resources.
3Productivity
If block family grouping is implemented to reduce calibration overhead, then processing efficiency is improved, but device complexity increases due to metadata management
Solution Approach 1:
The patent merges multiple blocks with similar characteristics into block families, managing them as a single unit for calibration purposes. This consolidation reduces the overall number of calibration operations needed while the metadata structure efficiently tracks family assignments, achieving processing efficiency gains that outweigh the metadata management overhead.
Data Source
AI summary
A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.