Memory Block Conductive Layer Separation for Stable GIDL Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently performing read, write, and erase operations due to variations in threshold voltages of select transistors caused by Gate Induced Drain Leakage (GIDL), which can lead to unstable operations and increased processing time.
Innovation Solution
The semiconductor memory device is designed with a conductive layer separated for each memory block, reducing capacitance and allowing for faster write operations. Additionally, the source-side select transistors are configured to enter an OFF state during read, verify, and erase operations, suppressing carrier exchange and stabilizing these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conductive layers are shared across memory blocks, then device complexity is reduced, but threshold voltage variations occur due to GIDL effects causing unstable operations
Solution Approach 1:
The conductive layers are segmented and separated for each memory block rather than being shared across all blocks. This segmentation isolates the GIDL effects to individual blocks, preventing threshold voltage variations from affecting other blocks, thereby improving operation stability while maintaining manageable device complexity
Solution Approach 2:
Each memory block is given locally optimized conductive layer characteristics through separation. The source-side select transistors in each block can be independently controlled to enter OFF state during specific operations, allowing local suppression of GIDL effects without impacting other blocks, thus resolving the stability issue
2Reliability
If conductive layers are separated for each memory block, then operation stability improves by suppressing GIDL effects, but device complexity increases
Solution Approach 1:
The conductive layers are segmented and separated for each memory block rather than being shared across all blocks. This segmentation isolates the GIDL effects to individual blocks, preventing threshold voltage variations from affecting other blocks, thereby improving operation stability while maintaining manageable device complexity
Solution Approach 2:
The separated conductive layer configuration serves multiple functions: it isolates GIDL effects, enables independent control of source-side select transistors, and allows flexible voltage application during read, verify, and erase operations. This multi-functionality justifies the increased complexity by delivering comprehensive operational stability
3Speed
If source-side select transistors remain ON during operations, then access speed improves, but carrier exchange increases causing unstable threshold voltages
Solution Approach 1:
The source-side select transistors dynamically change their state based on the operation being performed. During read, verify, and erase operations, they enter OFF state to suppress carrier exchange and stabilize threshold voltages. This dynamic control allows the system to prioritize stability when needed while maintaining the ability to switch to ON state for high-speed access operations
Solution Approach 2:
The source-side select transistors are periodically switched between ON and OFF states according to the operation sequence. This periodic control ensures that carrier exchange is suppressed at critical moments (read, verify, erase) while allowing high-speed access during appropriate phases, resolving the contradiction between speed and stability
Data Source
AI summary
A semiconductor memory device includes memory blocks arranged in a first direction and bit lines that are arranged in a second direction, and are arranged with the memory blocks in a third direction. The memory block includes first conductive layers arranged in the third direction, a second conductive layer disposed on a side opposite to the bit lines in the third direction with respect to the first conductive layers, semiconductor layers that extend in the third direction, are opposed to the first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the bit lines, and electric charge accumulating films disposed between the first conductive layers and the semiconductor layers. The first conductive layers and the second conductive layer are separated between the memory blocks.