Semiconductor Memory Device Block Insulating Layer Segmentation
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Solution Overview
Problem
Current semiconductor memory devices, particularly NAND type flash memory, face challenges in maintaining consistent electrical characteristics due to variations in etching processes during the manufacturing of memory cell arrays, leading to inconsistencies in memory cell performance.
Innovation Solution
The implementation of a semiconductor memory device structure that includes a memory cell array with a columnar semiconductor layer and a multi-film layer comprising a tunnel insulating layer, charge accumulation layer, block insulating layer, block high-permittivity layer, and barrier layer, where the block insulating layer has a first and second block insulating film to compensate for film thickness variations and reduce electrical characteristic variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single block insulating layer is used in the memory cell structure, then the device structure is simpler, but film thickness variations during etching cause electrical characteristic inconsistencies
Solution Approach 1:
The block insulating layer is divided into multiple sub-layers (first block insulating layer, second block insulating layer, third block insulating layer) with different thicknesses. This segmentation allows each sub-layer to contribute differently to the overall electrical characteristics, compensating for etching variations and improving consistency without requiring excessive total thickness.
Solution Approach 2:
The patent changes the thickness parameters of individual block insulating sub-layers to optimize electrical characteristics. By adjusting the thickness of each sub-layer independently, the design compensates for manufacturing variations and achieves more consistent electrical performance across different memory cells.
2Manufacturing precision
If the block insulating layer thickness is increased to compensate for etching variations, then electrical characteristic consistency improves, but the overall device size increases
Solution Approach 1:
Instead of using a single thick block insulating layer, the patent segments it into multiple thinner sub-layers. This achieves the necessary total thickness for electrical consistency while allowing better control over the cumulative thickness through independent formation processes for each sub-layer.
Solution Approach 2:
The block insulating layer is formed as a composite structure with multiple sub-layers that may have different material compositions or properties. This composite approach allows optimization of electrical characteristics without requiring uniform thickness throughout, thereby reducing the overall thickness requirement while maintaining consistency.
Data Source
AI summary
A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: an inter-layer insulating layer and a conductive layer stacked in a stacking direction; a columnar semiconductor layer having a side surface that faces side surfaces of the inter-layer insulating layer and the conductive layer and extending in the stacking direction; and a block insulating layer and a block high-permittivity layer disposed between the columnar semiconductor layer and the conductive layer, the block insulating layer including: a first block insulating film that covers a side surface of the columnar semiconductor layer from a lower surface of the inter-layer insulating layer to an upper surface of the conductive layer in the stacking direction; and a second block insulating film that contacts the first block insulating film and covers at least a side surface and a lower surface of the conductive layer.