Memory Block Addressing With Logical Mapping for NAND Bad Blocks
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Solution Overview
Problem
NAND flash memory devices often have initial bad blocks that limit their use due to insufficient partition memory, as they lack a controller to manage array blocks, leading to unusable chips when bad blocks are concentrated.
Innovation Solution
A block addressing method that converts physical addresses of memory blocks into logical addresses using a specific mapping rule, dividing the memory array into N partitions to disperse bad blocks and ensure sufficient valid blocks for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical addresses are used directly for block addressing, then the addressing is simple and direct, but initial bad blocks concentrate in critical regions causing insufficient partition memory
Solution Approach 1:
The patent divides the memory array into N partitions and segments the block addressing into multiple logical address spaces. Each partition receives a portion of the blocks, distributing bad blocks across different partitions rather than concentrating them in critical regions. This segmentation allows the system to maintain sufficient valid blocks in each partition for reliable data storage.
Solution Approach 2:
The patent introduces logical addresses as an intermediary layer between physical addresses and partition allocation. The mapping rule converts physical addresses to logical addresses, which then guide block assignment to partitions. This intermediary mechanism decouples the direct relationship between physical location and partition assignment, enabling bad blocks to be redistributed away from critical regions.
2Reliability
If a controller is added to manage array blocks, then bad blocks can be managed and distributed, but the device complexity increases and cost rises
Solution Approach 1:
The patent implements a self-service mechanism where the memory device automatically performs block-to-partition mapping using a predetermined mapping rule without requiring an external controller. The mapping logic is embedded in the memory device itself, allowing it to autonomously distribute blocks (including bad blocks) across partitions based on their physical addresses, eliminating the need for controller-based management.
Solution Approach 2:
The patent changes the addressing parameter from direct physical addresses to transformed logical addresses using a specific mapping rule. This parameter transformation enables the memory device to automatically redistribute blocks across partitions based on mathematical relationships between physical and logical addresses, achieving bad block management through parameter manipulation rather than controller intervention.
3Quantity of substance
If blocks are densely packed in critical regions, then the memory capacity is maximized, but the presence of initial bad blocks makes the chip unusable
Solution Approach 1:
The patent introduces a new dimension of organization by dividing memory into multiple partitions (spatial dimension) and using logical address spaces (addressing dimension). This multi-dimensional organization allows blocks to be distributed across partitions based on their physical addresses, ensuring that even with dense packing, bad blocks are spread across different partitions rather than concentrating in critical regions, maintaining chip usability.
Solution Approach 2:
The patent segments the memory array into N partitions, each capable of independently storing data. By segmenting the address space and physically distributing blocks across partitions, the system ensures that failures in one partition (due to bad blocks) do not render the entire chip unusable. Each partition maintains sufficient valid blocks to fulfill storage requirements.
Data Source
AI summary
A block addressing method for a memory device and a memory device are provided. The block addressing method includes: dividing a memory array in the memory device into N partitions, where N is an integer; converting a physical address of each of a plurality of blocks of the memory device into a logical address according to a specific mapping rule; and addressing the blocks to the N partitions according to the logical addresses.