Memory Block Mapping for Sub-Word Line Driver Fault Tolerance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices increase in capacity, the likelihood of defective memory cells increases, making it difficult to produce devices without errors, and existing error correction methods struggle to handle the maximum number of error bits caused by faults in sub-word line drivers.
Innovation Solution
A memory device and system that adjust the mapping between data pads and cell blocks sharing sub-word line drivers to control the number of bits output, using a mapping circuit to reduce the number of error bits within the error correction capability of the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The memory device is divided into multiple cell blocks (first cell block, second cell block, etc.) that share sub-word line drivers. This segmentation allows independent error management for each block, enabling the system to handle defects in high-capacity devices by treating them as manageable units rather than a monolithic problematic structure.
Solution Approach 2:
A mapping circuit is introduced as an intermediary component between the memory cell array and the data input/output circuit. This mapping circuit dynamically adjusts the mapping between cell blocks and data pads, enabling flexible data output configuration that can adapt to defective cells while maintaining high-capacity operation.
2Device complexity
If multiple cell blocks share sub-word line drivers, then device complexity is reduced, but the number of error bits increases beyond error correction capability
Solution Approach 1:
The mapping circuit provides dynamic reconfiguration capability, allowing the system to adjust the mapping between cell blocks and data pads in real-time. When a sub-word line driver fault is detected, the mapping can be dynamically changed to redistribute data output, ensuring that the number of error bits remains within the error correction capability of the memory controller.
Solution Approach 2:
The system changes the operational parameters by adjusting the number of bits output from each cell block sharing activated sub-word line drivers. The mapping circuit controls this parameter to ensure that even when multiple blocks share drivers (reducing complexity), the total error bits from any single driver failure remain correctable.
3Device complexity
If mapping between cell blocks and data pads is fixed, then device complexity is reduced, but adaptability to defects decreases
Solution Approach 1:
The mapping circuit implements dynamic mapping adjustment, transitioning from a fixed mapping to a flexible, reconfigurable mapping system. This allows the memory device to adapt its data output configuration based on detected defects, improving defect tolerance while maintaining manageable complexity through automated control.
Solution Approach 2:
The system incorporates feedback mechanisms where the mapping circuit receives information about sub-word line driver status and adjusts the mapping accordingly. This feedback loop enables automatic adaptation to defects, allowing the system to maintain high reliability without requiring complex manual reconfiguration.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of cell blocks, each cell block including a plurality of memory cells and sharing sub-word line drivers with adjacent cell blocks; a data input/output circuit configured to input and output data corresponding to the plurality of cell blocks through a plurality of data pads; and a mapping circuit disposed between the memory cell array and the data input/output circuit, and configured to control a mapping between the plurality of cell blocks and the plurality of data pads, while adjusting, according to an output control signal, a number of bits of data output from cell blocks sharing activated sub-word line drivers.