Memory Block Mapping Recovery for Uncorrectable Error Handling

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Solution Overview

Problem

Memory systems face performance degradation due to foreground mapping recovery operations, which cause latency and inefficiencies when uncorrectable errors occur during maintenance, such as garbage collection, leading to incorrect data transmission and block unavailability until mapping updates are completed.

Innovation Solution

Implementing a bad block table (BBT) with reserved indices allows mapping recovery operations to be performed in the background, enabling continued access to physical blocks while updating logical-to-physical mappings for blocks with errors, thus reducing latency and improving overall system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If mapping recovery operations are performed in the foreground, then data accuracy is improved by correcting uncorrectable errors, but system performance degrades due to latency and block unavailability

Engineering Contradiction:
Improvedata accuracyVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the mapping recovery process into background operations by introducing a bad block table with reserved indices. This allows the mapping recovery to be separated from foreground operations, enabling concurrent execution without blocking the main data access path.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bad block table is pre-initialized with reserved indices before maintenance operations begin. This preliminary setup enables the system to immediately redirect mapping recovery operations to background processing without delays, maintaining foreground performance while ensuring data accuracy through subsequent background corrections.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If mapping recovery operations are performed in the foreground, then mapping updates are completed accurately, but access time increases due to latency

Engineering Contradiction:
Improvemapping update accuracyVSAvoidaccess time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the mapping update process into two phases: foreground phase where data access occurs using current mappings, and background phase where inaccurate mappings are corrected using the bad block table. This segmentation eliminates the time penalty for mapping updates during data access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bad block table acts as an intermediary structure that stores mapping corrections separately. This intermediary allows the system to maintain accurate mappings without immediately updating all references, thereby reducing access time latency while ensuring mapping update accuracy through subsequent background processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If blocks with uncorrectable errors are made unavailable until mapping updates complete, then data integrity is ensured, but operational efficiency decreases

Engineering Contradiction:
Improvedata integrityVSAvoidoperational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces dynamic mapping management where the bad block table is updated in the background during maintenance operations. This dynamic approach allows blocks with uncorrectable errors to be gradually removed from the active mapping space without immediately halting operations, thus maintaining data integrity while improving operational efficiency through continuous background updates.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The bad block table is prepared in advance with reserved indices and mapping correction entries. This preliminary preparation enables the system to efficiently handle blocks with uncorrectable errors by redirecting them to background processing, ensuring data integrity is maintained while operational efficiency is preserved through pre-configured error handling mechanisms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250383994A1Logical block address recovery by a memory system
Publication Date: 2025.12.18 MICRON TECHNOLOGY INC
  • US20250383994A1 patent drawing
  • US20250383994A1 patent drawing
  • US20250383994A1 patent drawing

AI summary

Methods, systems, and devices for logical block address recovery by a memory system are described. A memory system may identify an uncorrectable error associated with a virtual block and may update an index of the virtual block from a first index (e.g., a first value) to a second index (e.g., a second value). The memory system may determine a logical block address of the virtual block that is associated with the uncorrectable error and may update a mapping (e.g., a logical-to-physical (L2P) mapping) between the logical block address and a physical block of the memory system.