Fine-Grained Memory Module Voltage Control for Data Retention
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Solution Overview
Problem
Current microcontroller systems waste power by applying a single voltage to all memory cells, even if only a few cells require higher voltages, leading to inefficiency in power consumption.
Innovation Solution
A system with multiplexors that dynamically switch between multiple voltage rails based on operational parameters of individual memory blocks, such as process corners, temperature, and operating modes, to minimize the voltage required for data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single high voltage is applied to all memory cells to ensure reliable data retention for worst-case bitcells, then data integrity is maintained, but power consumption increases significantly for all bitcells including those that could operate at lower voltages
Solution Approach 1:
The memory chip is divided into multiple segments or regions, each with its own voltage control. Instead of applying a uniform voltage to the entire chip, the system segments the memory into zones that can be independently voltage-controlled, allowing each segment to receive only the voltage necessary for its specific bitcell characteristics.
Solution Approach 2:
Different voltage levels are applied to different spatial locations or regions of the memory chip based on the local characteristics of bitcells in those regions. This ensures that each local area receives the appropriate voltage for its specific process corner and performance characteristics, rather than using a single conservative voltage for the entire chip.
2Reliability
If a single conservative voltage level is used for all memory blocks, then all bitcells can operate reliably at their worst-case process corner, but good bitcells waste power being operated at higher than necessary voltage levels
Solution Approach 1:
The voltage assignment system is dynamic rather than static. During manufacturing testing, each memory block is evaluated and assigned a specific voltage level based on its actual performance characteristics. This dynamic assignment allows the system to adapt to the actual quality of each memory block rather than using a fixed conservative voltage for all blocks.
Solution Approach 2:
The voltage parameter is changed and optimized for each individual memory block based on its measured characteristics. Instead of using a single voltage parameter for all blocks, the system determines and applies different voltage parameters to different blocks, matching the voltage to the actual performance capability of each block.
3Adaptability or versatility
If voltage is increased to meet worst-case process corner requirements, then all memory blocks can operate across all process variations, but power consumption increases for all blocks including those that could operate at lower voltages
Solution Approach 1:
The memory system is segmented into multiple voltage domains or regions, each optimized for specific process corner requirements. This segmentation allows different parts of the memory to operate at different voltage levels appropriate to their process characteristics.
Solution Approach 2:
The memory system achieves universal compatibility with multiple process corners through a multi-voltage architecture. By supporting multiple voltage levels and dynamically assigning appropriate voltages to different memory blocks, the system can accommodate various process variations without always operating at the highest voltage.
Data Source
AI summary
Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.