Memory Block Pairs With Interposed Read/Write Circuit
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Solution Overview
Problem
In three-dimensional memory cell arrays, securing an adequate arrangement pitch between bit lines coupled to channel layers is challenging, leading to insufficient arrangement margins and difficulties in integrating memory cells effectively.
Innovation Solution
The memory device incorporates a read/write circuit between two half memory blocks, allowing bit lines to be arranged in separate groups, with row decoder groups enabling simultaneous selection of memory block pairs using a single block selection signal, thereby increasing the degree of freedom in arranging bit lines and improving operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional memory cells are arranged with channel layers extending in the vertical direction, then the degree of integration of the memory cell array is increased, but the arrangement pitch between bit lines becomes insufficient
Solution Approach 1:
The memory block is divided into two half memory blocks (first half memory block and second half memory block) that are coupled to separate bit line groups. This segmentation allows bit lines to be arranged in distinct groups with adequate spacing, resolving the arrangement pitch issue while maintaining high integration through the three-dimensional structure.
Solution Approach 2:
The patent transitions from a conventional two-dimensional bit line arrangement to a three-dimensional configuration where bit lines are arranged in multiple groups at different spatial positions. By utilizing vertical stacking and horizontal separation of bit line groups, the design achieves both high integration and sufficient arrangement pitch.
2Productivity
If channel layers are arranged in a zigzag manner to increase integration, then the degree of integration is improved, but the arrangement margin of bit lines becomes insufficient
Solution Approach 1:
The zigzag channel layer structure is segmented into two half memory blocks that are independently coupled to separate bit line groups. This allows the bit lines to be positioned with adequate margins while the channel layers maintain their high-density zigzag arrangement for maximum integration.
Solution Approach 2:
The read/write circuit serves as an intermediary component positioned between the two half memory blocks. It facilitates data transfer between the separated bit line groups while allowing each group to maintain its own spatial arrangement with sufficient margins, thus mediating between the high integration requirement and the arrangement margin constraint.
3Productivity
If multiple bit lines are closely arranged to increase integration, then the degree of integration is improved, but parasitic capacitance increases
Solution Approach 1:
By dividing the bit lines into separate groups coupled to different half memory blocks, the patent reduces the density of bit lines in any single location. This spatial segmentation decreases the mutual capacitance between adjacent bit lines while preserving the overall high integration through the three-dimensional memory structure.
Data Source
AI summary
A memory device may include a first half memory block, a second half memory block, a row decoder group, and a read/write circuit which may be disposed between the first half memory block and the second half memory block. The read/write circuit may be coupled to the first half memory block and the second half memory block through a first bit line and a second bit line. The row decoder group may be configured to simultaneously select the first half memory block and the second half memory block in response to a single block selection signal.