Memory Block Partial Erase for Read Window and Endurance
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Solution Overview
Problem
Existing memory systems face issues with a decrease in read window budget (RWB) and reduced endurance of memory cells due to prolonged idle times between erase and write operations, which can be exacerbated by pre-erase schemes and deep erase operations.
Innovation Solution
Performing a partial erase operation in the background, consisting of a first subset of erase cycles before a write command and a second subset in response to the command, to mitigate RWB loss and enhance endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-erase schemes are used to proactively erase blocks during background operations, then write operation readiness is improved, but read window budget decreases and endurance is reduced
Solution Approach 1:
The patent divides the erase operation into two segments: a first subset of erase cycles performed during background operations to partially erase the block, and a second subset performed in response to a write command to complete the erasure. This segmentation allows the system to make progress on erasure during idle times without fully completing the operation, thereby maintaining better read window budget and endurance compared to traditional pre-erase schemes that fully erase blocks proactively.
Solution Approach 2:
The patent applies partial action by performing only a first subset of erase cycles during background operations rather than completing the full erase operation. This partial erasure is sufficient to improve write operation readiness compared to no pre-erase, while avoiding the excessive action of complete erasure that would harm read window budget and endurance. The remaining erase cycles are completed only when actually needed for a write operation.
2Reliability
If deep erase operations are performed to mitigate threshold voltage shifts, then read window budget is maintained, but endurance is significantly reduced
Solution Approach 1:
The patent performs a preliminary partial erasure operation during background operations, applying a first subset of erase cycles that begin to address threshold voltage shifts before a write operation is needed. This preliminary action reduces the magnitude of subsequent voltage shifts that would occur during idle times, thereby maintaining read window budget without requiring a full deep erase operation that would severely impact endurance. The approach proactively manages voltage drift with minimal wear.
3Reliability
If full erase operations are completed before write operations, then data integrity is ensured, but latency increases
Solution Approach 1:
The patent performs only a partial erasure (first subset of cycles) during background operations rather than completing the full erase operation. This partial action reduces the time required for the initial erasure phase, thereby reducing latency for subsequent write operations. The remaining erase cycles (second subset) are completed only when a write command is actually received, ensuring data integrity is maintained while minimizing unnecessary wait times during idle periods.
Data Source
AI summary
Methods, systems, and devices for an erase operation for a memory system are described. The memory system may perform, on a block of memory cells, a first portion of an erase operation. After performing the first portion of the erase operation, the memory system may receive a write command to write data to the block of memory cells. In response to receiving the write command, the memory system may determine whether a threshold voltage of the block of memory cells satisfies a threshold. In response to determining the that the threshold voltage satisfies the threshold, the memory system may perform a second portion of the erase operation on the block of memory cells. As such, the memory system may write the data to the block of memory cells in response to performing the second portion of the erase operation.