Memory Block Pool Wear Leveling via Relaxation Time Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wear leveling techniques in solid state drives (SSDs) do not effectively minimize the Bit Error Rate (BER) of NAND-based flash memory systems, leading to reduced data retention capacity and reliability over time due to cumulative changes in storage element characteristics from high voltage stress during program/erase cycles.
Innovation Solution
Implementing a method that identifies memory block pools and determines a relaxation time delay between program/erase cycles to minimize the bit error rate, where the relaxation time delay is the duration between a completed programming cycle and the point when the bit error rate of each memory block pool is at its minimum, allowing for a predetermined number of program/erase cycles to be executed based on this delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If conventional wear leveling techniques are used to evenly distribute P/E cycles among all blocks, then the useful life of the device is extended, but the Bit Error Rate (BER) of the data storage device increases
Solution Approach 1:
The patent divides the memory blocks into multiple pools (first pool, second pool, third pool) based on their BER characteristics. This segmentation allows different pools to be managed differently - the first pool undergoes aggressive wear leveling while the second and third pools receive reduced or no wear leveling, respectively. This resolves the contradiction by segmenting the uniform wear leveling approach to accommodate varying BER conditions across different blocks.
Solution Approach 2:
The patent applies local quality by treating different memory blocks differently based on their individual BER characteristics. Blocks with lower BER are placed in the first pool and receive full wear leveling treatment, while blocks with higher BER are placed in the second and third pools and receive reduced treatment. This localized differentiation allows the system to extend the useful life of low-BER blocks without compromising the reliability of high-BER blocks.
2Reliability
If the number of program/erase cycles is increased to improve data retention capacity, then the storage element reliability improves, but the cumulative permanent changes to storage element characteristics increase
Solution Approach 1:
The patent implements periodic action by introducing relaxation time delays between P/E cycles for different pools. The first pool experiences frequent P/E cycles for maintaining data retention, while the second and third pools experience reduced frequency due to relaxation delays. This periodic variation in cycling intensity allows the system to maintain data retention capacity while reducing cumulative stress on storage elements, particularly for pools with higher initial BER.
3Productivity
If high gate voltages are applied during P/E cycles to program/erase storage elements, then the programming and erasing operations are effective, but charge becomes trapped in the gate oxide through stress-induced leakage current
Solution Approach 1:
The patent converts the harmful effect of stress-induced leakage current into a beneficial feature by utilizing the relaxation time delay period. During this relaxation period, trapped charge in the gate oxide has time to dissipate through the leakage current path, effectively cleaning the harmful charge accumulation. This transforms the previously harmful SILC into a beneficial charge dissipation mechanism that reduces BER over time.
Data Source
AI summary
A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools.