Memory Block Power Loss Detection With Partial Block Offsets
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Solution Overview
Problem
Existing power loss error detection procedures in memory devices, particularly in multi-level cells, result in a high overkill rate due to shifts in threshold voltages caused by partial block phenomena, leading to unnecessary power, computing, and memory resource consumption.
Innovation Solution
Implementing a power loss error detection procedure that compensates for partial block-induced voltage shifts by using location-dependent read reference voltage offsets based on the location of the last written page within the block, reducing the overkill rate by accurately determining if the programming operation was completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional power loss error detection procedure is used in multi-level cell memory devices, then the error detection can identify programming completion, but the threshold voltage shifts caused by partial block phenomena result in a high overkill rate
Solution Approach 1:
The patent applies local quality by using location-dependent read reference voltage offsets that are specific to the last written page's position within the block. Instead of using a uniform detection method for the entire block, the system tailors the detection parameters to the specific local region where programming occurred, thereby reducing false positives caused by partial block phenomena while maintaining accurate error detection.
2Reliability
If a conventional power loss error detection procedure is used, then programming completion can be detected, but unnecessary power, computing, and memory resources are consumed due to high overkill rate
Solution Approach 1:
The patent changes the detection parameters by introducing location-dependent voltage offsets that are calculated based on the last written page's position. This parameter adjustment allows the error detection procedure to distinguish between actual programming failures and false indicators caused by partial block writes, thereby reducing unnecessary resource consumption while maintaining reliable detection.
3Loss of energy
If location-dependent read reference voltage offsets are used to compensate for partial block-induced voltage shifts, then the overkill rate is reduced, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the location-dependent voltage offsets in a lookup table during normal operation. This allows the error detection procedure to simply retrieve and apply the appropriate offset based on the last written page's location, rather than performing complex real-time calculations, thereby reducing operational complexity while maintaining the benefits of location-specific compensation.
Data Source
AI summary
In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.