Memory Block Pre-Erase Timing for Better Data Retention

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Solution Overview

Problem

Existing memory systems face challenges in maintaining read window budget (RWB) margin while complying with other system requirements, such as latency, especially when storing data in a powered-off state for extended periods, leading to potential data corruption.

Innovation Solution

Implementing techniques to pre-erase memory cells, particularly TLCs or QLCs, before programming to enhance RWB margin, ensuring they are erased for a threshold duration, thereby improving data retention without affecting other system properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory cells are erased before programming to improve RWB margin, then data retention is improved, but write operation time increases

Engineering Contradiction:

Improvedata retentionVSAvoidwrite operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by erasing memory blocks in advance before they are needed for programming operations. The controller identifies blocks that need to be erased and performs the erase operation prior to the write operation, ensuring the read window budget margin is improved without extending the actual write time. This is achieved by scheduling erase operations during idle periods or background processes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system performs self-service by automatically managing the erase operations without requiring explicit user intervention. The controller monitors the state of memory blocks and autonomously determines when pre-erasing is needed, selecting appropriate blocks for erasure, and executing the erase operations as part of the normal write workflow, thereby improving data retention transparently.

Inventive Principle:

Principle #25Self-service

2Reliability

If pre-erasing operations are performed to enhance RWB margin, then data retention in powered-off states is improved, but system complexity increases

Engineering Contradiction:

Improvedata retentionVSAvoidcontroller logic

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the memory space into different blocks and tracking their individual erase states. The controller maintains a data structure that segments the memory management logic, tracking which blocks have been pre-erased and their associated metadata. This segmentation allows the system to manage pre-erasing operations systematically without overwhelming complexity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system implements feedback mechanisms where the controller continuously monitors the state of memory blocks, determines when pre-erasing is necessary based on retention requirements, and adjusts its behavior accordingly. The controller receives feedback about block usage patterns and power-off durations, then adapts the pre-erasing strategy to balance data retention needs with system simplicity.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20260023485A1Pre-erasing memory blocks

Publication Date: 2026.01.22 MICRON TECHNOLOGY INC

AI summary

Methods, systems, and devices for pre-erasing memory blocks are described. Multiple memory cells of multiple available memory cells may be erased to obtain multiple erased memory cells. Subsequent programming of the multiple erased memory cells may be delayed for a duration. Based on delaying the subsequent programming of the multiple erased memory cells for the duration, the multiple erased memory cells may be programmed.