Memory Device Partially Written Block Read Trim Adaptation
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Solution Overview
Problem
Existing memory systems face challenges in efficiently handling partially written blocks, leading to increased uncorrectable bit error rates and complexity in system controllers due to cell-to-cell interference and inadequate read trim settings.
Innovation Solution
The method involves maintaining internal status of the last written page in a partially written block within the memory device, using page map information and trim sets to determine the appropriate read trim set for reading pages, thereby reducing errors and complexity by differentiating the treatment of the last written page from previously written pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform read trim settings are used for all pages in a block, then device complexity is reduced, but uncorrectable bit error rates increase due to cell-to-cell interference variations
Solution Approach 1:
The patent applies local quality by differentiating read trim settings based on the specific page being read within a block. Pages are categorized into different types (e.g., first page, intermediate pages, last page) and each type receives optimized read trim parameters tailored to its specific cell-to-cell interference characteristics, thereby improving reliability without requiring complex per-cell parameter management.
Solution Approach 2:
The patent segments the read operation into distinct phases corresponding to different page types within a block. By dividing the read process into segments (reading the first page with one trim setting, intermediate pages with another, and the last page with a third), the system achieves adaptive error correction without requiring a single complex parameter set for all pages.
2Reliability
If adaptive read trim settings are used for different pages, then bit error rates are reduced, but system controller complexity increases
Solution Approach 1:
The memory device performs self-service by autonomously determining the appropriate read trim settings based on internally tracked block and page status information. The device automatically identifies which page type is being read and applies the corresponding optimized trim parameters without requiring external controller intervention or complex coordination, thereby reducing system controller complexity while maintaining adaptive error correction.
Solution Approach 2:
The patent implements feedback mechanisms where the memory device continuously tracks the state of blocks and pages (e.g., which pages have been programmed, block wear status) and uses this feedback information to automatically select appropriate read trim settings. This closed-loop approach enables adaptive error correction with simplified control logic.
3Reliability
If corrective reads are performed to reduce errors, then data accuracy improves, but read latency increases
Solution Approach 1:
The patent applies preliminary action by pre-determining and storing optimized read trim settings for different page types before actual read operations occur. The system prepares the appropriate trim parameters in advance based on block and page status, so that during read operations, the correct parameters are immediately available without requiring iterative corrective reads, thereby reducing read latency while maintaining data accuracy.
Data Source
AI summary
The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.