Memory Block Redundancy via Sequential Address Translation
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Solution Overview
Problem
Existing memory devices face challenges in efficiently compensating for voltage delays in NAND flash memory arrays due to the placement of redundant blocks, which can lead to errors in data access when defective blocks are replaced, as the host controller's compensation is based on the location of the defective block rather than the actual location of the redundant block.
Innovation Solution
A novel redundancy scheme where the controller increments the addresses of non-defective blocks sequentially to replace defective blocks with proximate non-defective blocks closer to the defective ones, allowing for accurate voltage delay corrections based on the actual location of the replacement blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant blocks are placed in a different portion of the memory array to replace defective blocks, then defective blocks can be replaced, but voltage delay compensation errors occur because the host controller compensates based on the defective block location rather than the redundant block location
Solution Approach 1:
The patent introduces an address translation mechanism as an intermediary between the host controller and the memory array. The translation layer maps defective block addresses to redundant block addresses, allowing the host controller to use simple address increments while the translation mechanism handles the complex mapping to ensure accurate voltage delay compensation at the actual redundant block location
Solution Approach 2:
The patent changes the address parameter representation by maintaining multiple address spaces: the host controller uses simplified incremented addresses, while the memory array uses actual physical addresses that account for the location of redundant blocks. This parameter transformation enables both simple host operations and accurate voltage delay compensation
2Measurement precision
If addresses of non-defective blocks are incremented sequentially to replace defective blocks, then voltage delay corrections become more accurate, but address management complexity increases
Solution Approach 1:
The patent performs preliminary address translation setup during manufacturing or initialization, where the mapping between host addresses and physical memory addresses is pre-determined and stored. This preliminary action allows the host controller to use simple sequential address increments without needing to understand the complex physical layout or perform real-time calculations
Solution Approach 2:
The patent creates a virtual address space that copies the simplicity of sequential addressing while maintaining a separate physical address space that reflects the actual memory layout with redundant blocks. The address translation mechanism acts as a copy or mapping layer that translates between these two address spaces, hiding the complexity from the host controller
Data Source
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AI summary
Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device (100) receives an external address that addresses a non-defective memory block (2103) of a sequence of memory blocks (210) of the memory device (100) in place of a defective memory block (2102) of the sequence of memory blocks (210) such that the non-defective memory block (2103) replaces the defective memory block (2102). The non-defective memory block (2103) is a proximate non-defective memory block following the defective memory block (2102) in the sequence of memory blocks (210) that is available to replace the defective memory block (2102).