Memory Device Block Region Segmentation for Program Speed Consistency
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Solution Overview
Problem
Current memory devices face inefficiencies in operation due to variations in channel hole diameters across different blocks within a memory cell region, leading to inconsistent program and erase speeds, which can degrade overall performance if a single bias condition is applied regardless of block positions.
Innovation Solution
The memory device divides blocks into distinct regions based on their distance from the edges of the cell region, applying different bias sets to each region to compensate for variations in channel hole diameters, optimizing operation parameters for program, erase, and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single bias condition is applied to all blocks in the memory cell region, then the device complexity is reduced and ease of operation is improved, but the program and erase speeds become inconsistent across different blocks due to variations in channel hole diameters
Solution Approach 1:
The memory cell region is divided into multiple block regions based on distance from edges, with each region receiving tailored bias conditions. This segmentation allows different blocks to be operated with optimized parameters matching their specific characteristics, resolving the speed consistency issue while maintaining manageable complexity through systematic regional grouping.
Solution Approach 2:
Different bias conditions are applied to different block regions according to their specific characteristics (edge-proximity vs. center-position). Blocks in edge-proximity regions receive one set of bias conditions while center blocks receive another, ensuring each region operates under locally optimized conditions that match their channel hole diameter variations.
2Productivity
If different bias sets are applied to different block regions, then the program and erase speeds are optimized for each region, but the device complexity increases due to multiple operation parameter sets
Solution Approach 1:
By dividing the memory cell region into distinct block regions with clear spatial boundaries (edge-proximity vs. center), the complexity of managing multiple bias sets is reduced. Each segment has well-defined characteristics that allow systematic parameter assignment, making the complexity manageable through structured regional differentiation.
Solution Approach 2:
The patent systematically varies operation parameters (bias conditions) according to block region characteristics. By establishing clear parameter sets for different regions and linking them to specific spatial locations, the complexity is organized into a predictable pattern rather than arbitrary variations, facilitating easier management and control.
3Productivity
If blocks are divided into multiple regions with different bias sets, then the operational efficiency is enhanced, but the ease of operation decreases due to more complex control requirements
Solution Approach 1:
The memory device is segmented into block regions that can be independently controlled with appropriate bias sets. This segmentation enables parallel operation of different regions with optimized parameters, improving overall efficiency while the clear spatial definition of regions makes the control logic more systematic and manageable.
Solution Approach 2:
Each block region is configured with locally optimized bias conditions matched to its specific characteristics. This local optimization improves operational efficiency by ensuring each region operates at peak performance, while the systematic approach to regional differentiation provides a framework that simplifies control compared to attempting uniform optimization across all blocks.
Data Source
AI summary
A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.