Nonvolatile Memory Block Segmentation for Control Efficiency
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Solution Overview
Problem
Current three-dimensional NAND flash memory devices face challenges in increasing capacity while maintaining efficient control and reducing unintended programming in non-selected cells, as the block size is limited by the arrangement of bit lines and selection gate lines.
Innovation Solution
The proposed nonvolatile semiconductor memory device employs a structure where multiple bit lines are grouped into bundles and correspond to stacked memory strings, allowing for simultaneous selection and reduced block size, thereby increasing the number of blocks and improving control over the Vertical Gate NAND (VGNAND) by a memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the block size is increased to accommodate more memory cells, then the memory capacity is improved, but the control efficiency and ability to prevent unintended programming in non-selected cells deteriorates
Solution Approach 1:
The patent divides the selection transistor group into multiple selection transistor sub-groups, where each sub-group is associated with a specific bit line contact. This segmentation allows the memory controller to selectively control smaller blocks of memory cells through individual bit line contacts, improving control efficiency while maintaining overall memory capacity. The block size is effectively reduced by associating each bit line contact with a specific sub-group of selection transistors rather than controlling all selection transistors through a single bit line.
2Quantity of substance
If more bit lines are used to control more memory strings, then the memory capacity is improved, but the complexity of the device structure increases
Solution Approach 1:
The patent introduces a vertical dimension to the bit line structure by forming bit line contacts that extend in the vertical direction to connect with selection transistor sub-groups at different heights. This three-dimensional arrangement allows multiple bit lines to control memory strings stacked vertically, increasing memory capacity without proportionally increasing planar structure complexity. The bit line contacts serve as vertical interconnects that organize the selection transistor sub-groups in the vertical dimension.
Data Source
AI summary
According to the present embodiment, a nonvolatile semiconductor memory device includes a memory string group including k stacked memory strings, each of the memory strings including a plurality of nonvolatile memory cells connected in series, a selection transistor group including k selection transistors, each of the k selection transistors corresponding to each of the k memory strings respectively, the selection transistor group divided into n selection transistor sub-groups, each of the n selection transistor sub-groups including k/n selection transistors, n bit lines arranged in parallel to each of the k memory strings, and n bit line contacts arranged perpendicularly, each of the n bit line contacts connected to each of the n bit lines, respectively, each of the n bit line contacts connected to the k/n selection transistors belonging to the each of the n selection transistor sub-group respectively.