Memory System Block Segmentation for Bad Region Management

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Solution Overview

Problem

In NAND flash memory systems, the existing technologies face challenges in efficiently managing and utilizing memory cells, leading to reduced storage capacity and yield rates due to failures in memory blocks, which results in unnecessary reductions in storage capacity and increased manufacturing costs.

Innovation Solution

A memory system that manages data in cell units, executing write operations in page units and performing read operations to determine error correction capabilities for each page, allowing for the identification of good and bad pages, thereby preventing the entire block from being set as a bad block and optimizing storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If memory blocks are managed as complete units, then simplicity of management is improved, but storage capacity is reduced due to entire blocks being marked bad when any cell fails

Engineering Contradiction:
Improvemanagement simplicityVSAvoidstorage capacity
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent segments a memory block into multiple memory regions, each independently manageable. When a failure occurs in one region, only that specific region is marked as bad rather than the entire block, allowing other regions to remain usable and thereby preserving storage capacity while maintaining manageable granularity through regional division

Inventive Principle:
Principle #1Segmentation

2Reliability

If entire blocks are marked bad due to cell failures, then reliability is improved by ensuring only functional blocks are used, but manufacturing cost increases due to reduced yield

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

By dividing blocks into smaller regions with independent bad region management, the patent enables more precise fault isolation. This segmentation allows functional regions to be preserved and utilized, increasing the number of usable memory devices from production batches and thereby improving manufacturing yield and reducing per-unit costs while maintaining reliability through careful region selection

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent recovers usable capacity by discarding only the specific failed regions rather than entire blocks. Through the bad region management table and selective region marking, functional memory regions are recovered and made available for use, increasing effective yield from manufactured batches without compromising data integrity in selected regions

Inventive Principle:
Principle #34Discarding and recovering

3Quantity of substance

If fine-grained region management is implemented, then storage capacity utilization is improved, but device complexity increases due to additional management structures

Engineering Contradiction:
Improveusable storage capacityVSAvoidmanagement structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments blocks into regions and implements a bad region management table that tracks failed regions at the region level rather than block level. This segmentation enables finer-grained utilization of storage capacity by allowing selective use of functional regions while maintaining relatively simple management through the regional division scheme and associated tracking structure

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10803954B2Memory system
Publication Date: 2020.10.13 KIOXIA CORP
  • US10803954B2 patent drawing
  • US10803954B2 patent drawing
  • US10803954B2 patent drawing

AI summary

A memory system includes a memory unit with a plurality of first memory cells connected to a first word line and a memory controller to control the memory unit to write data in page units equal in size to the number of first memory cells. The memory unit is configured to write a plurality of pages of data to the plurality of first memory cells and then read each page of data thus written. The memory controller determines whether or not each page of data, as read from the plurality of first memory cells, satisfies a predetermined condition, and registers a determination result for each page indicating whether the predetermined condition was satisfied.