Semiconductor Memory Device Block Segmentation Voltage Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining optimal threshold voltage distribution due to electron trapping in unselected memory blocks during program operations, which affects the performance and reliability of memory cells.
Innovation Solution
The semiconductor memory device incorporates a power supply unit, switching circuit, and pass circuit to apply specific operating voltages and control signals, ensuring that unselected memory blocks are in a floating state or receive lower voltages, preventing electron trapping and improving threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If program operation is performed on selected memory block, then data can be programmed into memory cells, but electrons may be trapped in unselected memory blocks causing threshold voltage distribution degradation
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block and second memory block), each with independent global lines and internal global lines. This segmentation allows selective programming of one block while isolating others, preventing electron trapping in unselected blocks during program operations.
Solution Approach 2:
Switching circuits are introduced as intermediary components between global lines and internal global lines. These switching circuits control the electrical connection states, enabling the system to isolate unselected memory blocks by controlling switch states based on block selection signals, thereby preventing electron trapping while maintaining programming capability in selected blocks.
2Productivity
If multiple memory blocks are operated simultaneously, then productivity increases, but electron trapping in unselected blocks degrades threshold voltage distribution
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block and second memory block), each with independent global lines and internal global lines. This segmentation allows selective programming of one block while isolating others, preventing electron trapping in unselected blocks during program operations.
Solution Approach 2:
The switching circuits dynamically change connection states based on block selection signals. When a memory block is selected for programming, the switching circuits establish electrical connections for that block while disconnecting others, creating dynamic isolation that prevents electron trapping in unselected blocks during simultaneous operations.
3Ease of manufacture
If conventional programming is applied to entire memory array, then programming simplicity is maintained, but threshold voltage distribution deteriorates due to electron trapping in unselected blocks
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block and second memory block), each with independent global lines and internal global lines. This segmentation allows selective programming of one block while isolating others, preventing electron trapping in unselected blocks during program operations.
Solution Approach 2:
Different regions of the memory array (selected vs. unselected blocks) are given different electrical characteristics. The selected block receives programming voltages and signals, while unselected blocks are isolated through switching circuits, creating local quality differences that prevent electron trapping in unselected regions while maintaining overall programming functionality.
Data Source
AI summary
A semiconductor memory device includes a memory unit including a first memory block and a second memory block, a power supply unit suitable for applying a plurality of operating voltages to one of first global lines or second global lines, a switching circuit suitable for switching the first global lines and first internal global lines in response to a first control signal and switching the second global lines and second internal global lines in response to a second control signal, and a pass circuit suitable for electrically connecting the first internal global lines to word lines and selection lines of the first memory block and electrically connecting the second internal global lines to word lines and selection lines of the second memory block in response to a block selection signal.


