Memory Block Selection for SSD Wear Leveling

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Solution Overview

Problem

Memory block selection in solid state drives (SSDs) often results in uneven wear across memory units, leading to reduced lifetime due to frequent use of certain physical blocks while others remain underutilized, causing uncorrectable write and erase errors.

Innovation Solution

A memory controller is configured to organize physical blocks into Super Blocks across multiple Groups of planes, allowing it to dynamically assign unassigned logical block addresses to free Super Blocks based on available space, promoting even wear through round-robin allocation and tracking of free Super Blocks across multiple Groups.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory blocks are selected using conventional methods, then write operations can be performed quickly, but uneven wear occurs across memory units leading to reduced lifetime

Engineering Contradiction:
Improvewrite operation speedVSAvoidmemory unit lifetime
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory units are divided into multiple groups, and the patent implements round-robin allocation across these groups. This segmentation allows the system to distribute write operations systematically across different memory unit groups, preventing any single group from being overused and thereby extending overall system lifetime while maintaining write speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically tracks the number of free super blocks in each group and adapts the allocation strategy based on current wear levels and availability. This dynamic adjustment ensures that write operations are distributed evenly over time, balancing performance requirements with wear leveling to extend memory unit lifetime.

Inventive Principle:
Principle #15Dynamics

2Speed

If certain physical blocks are frequently used for write operations, then write speed is maintained, but uncorrectable write and erase errors increase due to premature wear

Engineering Contradiction:
Improvewrite speedVSAvoiderror rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements periodic allocation of physical blocks to logical block addresses using round-robin scheduling. This periodic action ensures that no single physical block is repeatedly used for writes, distributing wear uniformly across all blocks and reducing the frequency of uncorrectable errors while maintaining write speed.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system continuously monitors the wear status and free block availability of each memory unit group, using this feedback to dynamically adjust allocation decisions. This feedback mechanism prevents any group from reaching critical wear levels too quickly, reducing error rates while sustaining write performance.

Inventive Principle:
Principle #23Feedback

3Device complexity

If memory blocks are not evenly distributed, then allocation is simpler, but wear leveling is poor leading to reduced SSD lifetime

Engineering Contradiction:
Improveallocation complexityVSAvoidSSD lifetime
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

By segmenting memory units into groups and implementing round-robin allocation within each group, the patent creates a systematic yet simple allocation scheme. This approach achieves excellent wear leveling without requiring complex allocation algorithms, as the segmented structure naturally distributes writes evenly across all groups.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses dynamic tracking of free super blocks and adaptive allocation that responds to current system state. This dynamic approach simplifies management by automatically balancing wear across groups based on real-time conditions, extending SSD lifetime without imposing significant allocation complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP2404239B1Memory block selection
Publication Date: 2018.12.12 MICRON TECHNOLOGY INC
  • EP2404239B1 patent drawingFigure 1
  • EP2404239B1 patent drawingFigure 2
  • EP2404239B1 patent drawingFigure 3

AI summary

The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.