Memory Block Programming With Selective Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing storage devices face issues with data writing reliability, performance, and power consumption efficiency, particularly during program operations in memory cells.
Innovation Solution
The storage device employs a controller that applies a program voltage without a verification voltage in a first period for certain memory cells, followed by applying a verification voltage in a second period for other memory cells within the same storage block, using distinct program commands to optimize the program operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a verification voltage is applied after every program voltage to all memory cells, then the reliability of data writing is improved, but the power consumption increases and the writing performance deteriorates
Solution Approach 1:
The patent applies different program operations to different memory cells based on their specific characteristics. Some memory cells receive only a program voltage (first program operation) while others receive both program voltage and verification voltage (second program operation). This local differentiation allows the system to maintain reliability for cells that need it while reducing power consumption for cells that don't require verification.
Solution Approach 2:
The patent segments the memory cells into different groups based on their program operation requirements. The memory cells are divided into those that complete programming without verification and those that require verification. This segmentation enables selective application of verification voltages, optimizing the balance between reliability and power consumption.
2Reliability
If a verification voltage is applied after every program voltage to all memory cells, then the reliability of data writing is improved, but the writing performance deteriorates due to increased operation time
Solution Approach 1:
The patent implements local quality by applying verification operations only to specific memory cells that require it, rather than uniformly to all cells. This allows the system to maintain high writing performance for cells that don't need verification while ensuring reliability for cells that do require it.
Solution Approach 2:
The patent segments the program operation process into two distinct paths: a fast path for cells that complete programming without verification and a verified path for cells that require verification. This segmentation enables the system to achieve high overall writing performance while maintaining reliability for critical cells.
3Reliability
If the program operation is performed for a longer period to ensure complete programming, then the reliability is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic program operation durations based on individual memory cell characteristics. Some memory cells are programmed for a shorter period without verification, while others receive extended programming with verification. This dynamic adjustment optimizes the balance between reliability and power consumption by matching the program duration to the specific needs of each memory cell.
Solution Approach 2:
The patent changes the program operation parameters (voltage application duration and verification timing) based on memory cell characteristics. By adjusting these parameters dynamically, the system achieves reliable programming while minimizing power consumption, avoiding the need to extend program duration for all cells uniformly.
Data Source
AI summary
A storage device is capable of reducing the time required for a program operation, improving the efficiency of the program operation, and preventing the reliability of the program operation from being reduced by selectively performing a program operation without a verification operation or performing the program operation while performing the verification operation on a memory area included in a designated storage block of the memory.