3D Memory Block Silicide Contacts for Reliable Tier Access
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with reliable electrical access and isolation, particularly in the formation of NAND architecture, where the stair-step structure and contact regions require precise electrical access and insulation to maintain data storage over extended periods.
Innovation Solution
The method involves forming a memory array with laterally-spaced memory blocks comprising a vertical stack of alternating insulative and conductive tiers, where channel-material strings extend through these tiers, and metal silicide is formed along the conductive tiers to ensure reliable electrical coupling, with intervening insulating material providing lateral isolation between blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If vertically-stacked memory cells are formed with stair-step structure, then data storage retention is improved, but electrical access reliability deteriorates due to contact region isolation challenges
Solution Approach 1:
The memory array is divided into multiple independently formed memory blocks, each with its own contact regions and electrical access paths. This segmentation allows electrical connections to be established and maintained in each block independently, preventing isolation issues from affecting the entire array while maintaining data retention across all blocks.
Solution Approach 2:
The patent transitions from planar memory architecture to vertically-stacked three-dimensional architecture. Memory cells are stacked in multiple tiers along the vertical dimension, with conductive tiers and insulative tiers alternating to provide electrical access and isolation. This dimensional change increases storage density while maintaining electrical reliability through the vertical stacking approach.
2Quantity of substance
If vertically-stacked memory structure is implemented, then storage density is improved, but manufacturing precision requirements worsen due to complex tier formation
Solution Approach 1:
Conductive tiers and insulative tiers are formed in a predetermined alternating sequence during the manufacturing process. The conductive tiers are prepared in advance with appropriate materials and configurations, and insulative tiers are similarly pre-formed, allowing precise alignment and connection when stacked together. This preliminary preparation of individual tiers simplifies the overall assembly process while maintaining high precision.
Solution Approach 2:
The patent employs different material parameters and physical states for conductive versus insulative tiers. Conductive tiers use materials with high electrical conductivity, while insulative tiers use materials with appropriate dielectric properties. By changing material parameters systematically across tiers, the manufacturing process achieves the required precision through material properties rather than relying solely on geometric precision.
3Reliability
If contact regions are formed for electrical access, then electrical connectivity is improved, but insulation between blocks deteriorates due to proximity of conductive structures
Solution Approach 1:
Insulative tiers are positioned between adjacent conductive tiers and memory blocks to act as intermediary elements. These insulative layers physically separate conductive structures from different blocks, preventing electrical interference and crosstalk while allowing each block to maintain its own electrical connectivity through the conductive tiers. The insulative material serves as a mediator that enables both connectivity and isolation simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical accessibility and retention of data in memory cells, improving the reliability and longevity of memory arrays by ensuring robust electrical connections and insulation within the vertically-stacked structure.
Implementation Method 1
The silicon and the metal are reacted to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.