3D Memory Block Layout With Smaller Spare Blocks for Higher Integration
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Solution Overview
Problem
Existing memory devices face challenges in achieving high integration due to the reduced degree of integration caused by the allocation of spare blocks with the same area as main blocks, which leads to inefficient use of space.
Innovation Solution
The memory device is designed with a spare block having a smaller area than main blocks, allowing for a more efficient use of space by reducing the length and number of string selection lines, and integrating peripheral circuits more effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spare blocks are allocated with the same area as main blocks, then reliability is improved, but the degree of integration deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the area of spare blocks from main blocks. Specifically, spare blocks are designed with smaller areas (e.g., 1/4 or 1/2 the area of main blocks) since they only need to store backup data for a portion of the memory device. This localized optimization allows the system to maintain reliability while reducing overall space consumption, as each spare block is sized appropriately for its specific backup function rather than uniformly matching main block sizes.
2Area of stationary object
If spare blocks have smaller area, then the degree of integration is improved, but the number of string selection lines increases
Solution Approach 1:
The patent applies merging by consolidating the control of multiple spare blocks under shared string selection lines. Instead of providing dedicated string selection lines for each spare block, the invention enables multiple spare blocks to share common string selection lines through multiplexing and selective activation. This reduces the total number of string selection lines required, as the system can time-multiplex the shared lines across different spare blocks based on operational needs.
Solution Approach 2:
The patent applies universality by designing string selection lines that serve multiple functions - they control both main blocks and spare blocks, and can be dynamically allocated to different blocks depending on the operation. The string selection lines are not dedicated to a single block type but can universally address any block in the memory device, reducing the total line count while maintaining full functionality.
3Area of stationary object
If spare blocks have smaller area, then space utilization is improved, but the layout complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory device into distinct regions with different block size configurations. Main blocks maintain their full size for primary data storage, while spare blocks are segmented into smaller units positioned in available spaces between main blocks. This segmented approach allows flexible space utilization and simplifies the overall layout by creating a modular structure where different block types can be systematically arranged.
Solution Approach 2:
The patent applies dimensionality change by utilizing the two-dimensional layout space more efficiently. Instead of arranging all blocks in a uniform grid, the invention places smaller spare blocks in the interstitial spaces between larger main blocks, effectively using the available space in both dimensions. This approach transforms the layout from a simple rectangular arrangement to a more complex but space-efficient two-dimensional optimization.
Data Source
AI summary
A memory device includes a cell region in which memory blocks, respectively including gate electrodes and insulating layers, alternately stacked on a substrate, and channel structures, extending in a first direction, perpendicular to an upper surface of the substrate, passing through the gate electrodes and the insulating layers, and connected to the substrate, are arranged. A peripheral circuit region includes a row decoder connected to the gate electrodes and a page buffer connected to the channel structures. The memory blocks include main blocks and at least one spare block, wherein a length of the spare block is shorter than a length of each of the main blocks, in a second direction, parallel to the upper surface of the substrate.