Non-Volatile Memory Block Switching via Charge Sharing
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Solution Overview
Problem
Current non-volatile memory devices, such as NAND flash memory cards, face challenges in cost, energy consumption, and performance due to the limitations of two-dimensional arrays, and three-dimensional arrays have not fully optimized the transition between active and inactive states for memory blocks, leading to inefficiencies in read and write operations.
Innovation Solution
Implementing a memory block switching technique where charge sharing between memory blocks improves performance and reduces energy consumption by enabling efficient transitions between active and inactive states, allowing for shared and split decoders to optimize the layout and reduce signal conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If charge sharing is implemented between memory blocks during state transitions, then energy consumption is reduced and performance is improved, but device complexity increases due to the need for additional control circuits and coordination mechanisms
Solution Approach 1:
The system performs preliminary actions by pre-charging bit lines and preparing control signals before memory block switching occurs. The controller anticipates the need for charge sharing and initiates the appropriate control sequences in advance, reducing the energy required during actual block transitions while managing complexity through proactive coordination.
Solution Approach 2:
Control circuits act as intermediaries between memory blocks, coordinating the charge sharing process. These intermediary circuits manage the transfer of charge between blocks during state transitions, enabling efficient energy utilization while containing the complexity of coordination within dedicated control logic rather than requiring complex direct interactions between blocks.
2Productivity
If memory blocks transition efficiently between active and inactive states through charge sharing, then operational performance improves, but the complexity of controlling and coordinating the switching process increases
Solution Approach 1:
The system dynamically adjusts control signals and charge transfer timing based on the current state of memory blocks. The controller adapts the switching sequence and charge sharing parameters in real-time, enabling efficient transitions while managing complexity through dynamic rather than static control, allowing the system to optimize performance based on actual operational conditions.
Solution Approach 2:
The controller incorporates feedback mechanisms to monitor the state of memory blocks and adjust control signals accordingly. This feedback enables precise coordination of charge sharing during block transitions, improving operational performance while containing switching control complexity through intelligent regulation rather than overly complex predetermined sequences.
3Quantity of substance
If three-dimensional memory arrays are used to increase storage capacity, then manufacturing cost may be reduced, but the complexity of managing active and inactive block states increases
Solution Approach 1:
The three-dimensional memory array is segmented into multiple independently controllable memory blocks arranged in vertical layers. Each block can be independently activated or deactivated, allowing the system to manage state complexity through hierarchical segmentation. This segmentation enables efficient charge sharing between blocks while maintaining the high storage capacity provided by the three-dimensional architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This technique enhances the performance and reduces energy consumption by enabling efficient transitions between memory block states, improving the overall efficiency of memory operations and layout optimization.
Implementation Method 1
The transitioning of the second memory block from the inactive state to the active state includes sharing charge between the plurality of control lines of the first memory block and the plurality of control lines of the second memory block
Data Source
AI summary
A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.