Memory Block Trap-Up Recovery via De-Bias Voltage Adjustment
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Solution Overview
Problem
Memory systems face inefficiencies in managing trap-up conditions, leading to unnecessary block retirement and increased overhead, as high-VT select lines are identified and retired without attempts to recover or extend their operational life.
Innovation Solution
Modifying the high-VT scanning operation to identify and apply a lowered de-bias voltage to high-VT dummy word lines, assessing whether threshold voltage characteristics can be improved, and if so, maintaining or returning blocks to operational status, or marking them for limited use based on program and erase cycle thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-VT select lines are identified and blocks are retired immediately, then reliability is improved by removing defective blocks, but productivity deteriorates due to unnecessary block retirement and increased overhead
Solution Approach 1:
The patent applies preliminary action by performing a scan operation before block retirement to identify high-VT select lines and determine their cause. This preliminary investigation allows the system to distinguish between recoverable and non-recoverable blocks, preventing premature retirement and improving productivity while maintaining reliability through targeted retirement of only truly defective blocks.
Solution Approach 2:
The patent changes the parameter of block management by introducing a new state classification system that distinguishes between blocks with high-VT select lines due to trap-up conditions (recoverable) versus other failures (non-recoverable). This parameter change enables differentiated handling strategies, allowing recovery attempts for trap-up blocks while immediately retiring only confirmed defective blocks, thus optimizing both reliability and productivity.
2Device complexity
If blocks are retired without recovery attempts, then device complexity is reduced by simplifying management, but loss of substance increases due to unnecessary block retirement
Solution Approach 1:
The patent implements feedback by introducing a scan operation that continuously monitors select line threshold voltages and provides information about trap-up conditions. This feedback mechanism enables the system to adjust block management decisions dynamically, attempting recovery for blocks with recoverable trap-up conditions while maintaining simplified management for confirmed defective blocks, thus reducing unnecessary block retirement.
Solution Approach 2:
The patent applies discarding and recovering by differentiating between blocks that should be immediately retired versus blocks that can be recovered. Blocks with high-VT select lines caused by trap-up conditions are candidates for recovery through modified program/erase cycles, while blocks with other types of failures are discarded. This selective approach reduces loss of substance by recovering usable blocks while maintaining device complexity management through clear classification criteria.
3Ease of operation
If standard program and erase cycles are used without modification, then ease of operation is maintained, but trap-up conditions worsen due to continued charge trapping
Solution Approach 1:
The patent applies periodic action by implementing modified program and erase cycles that are periodically applied to blocks identified with high-VT select lines. These periodic recovery cycles use specific voltage sequences (including reduced de-bias voltages) to attempt charge removal from trap sites. The periodic nature allows the system to maintain normal operation for most blocks while periodically addressing trap-up conditions in affected blocks, balancing ease of operation with trap-up mitigation.
Data Source
AI summary
Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.