Memory Block Read Voltage Offsets for Partial Programming Errors
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Solution Overview
Problem
Existing implementations fail to adequately address the increased bit error rates in partially programmed blocks of memory devices due to temporal voltage shifts and cell-to-cell interference, leading to higher page raw bit error rates and data degradation.
Innovation Solution
Implementing an adaptive block family error avoidance scheme that tracks temporal voltage shifts for partially programmed blocks grouped by block families and applies appropriate voltage offsets based on block affiliation, using sub-BFEA offset lookup tables to improve read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read operations are used for partially programmed blocks, then device simplicity is maintained, but bit error rates increase significantly
Solution Approach 1:
The patent applies different read operations based on the local characteristics of memory blocks. Specifically, it identifies partially programmed blocks through metadata and applies specialized read operations only to those blocks, while conventional read operations continue to be used for fully programmed blocks. This localized approach reduces bit error rates in affected areas without requiring system-wide complexity changes.
Solution Approach 2:
The patent performs preliminary identification of partially programmed blocks using metadata before executing read operations. By pre-determining which blocks require special handling through the presence of partial programming indicators in metadata, the system prepares appropriate read operations in advance, preventing bit errors before they occur during data retrieval.
2Reliability
If error recovery mechanisms are deployed to handle bit errors, then data reliability improves, but performance penalties increase
Solution Approach 1:
The patent converts the harmful effect of partial programming (which causes bit errors) into a beneficial classification system. By using metadata to identify partially programmed blocks, the system creates a structured approach that prevents errors through targeted read operations rather than relying on error recovery mechanisms, thereby improving reliability without performance penalties.
3Measurement precision
If block family error avoidance tracking is implemented, then read operation accuracy improves, but system overhead increases
Solution Approach 1:
The patent tracks temporal voltage shifts selectively for partially programmed blocks grouped by block families, rather than monitoring all blocks uniformly. This localized tracking approach uses metadata to identify which blocks require monitoring and applies voltage offset corrections only where needed, improving read accuracy for affected blocks while minimizing system overhead.
Solution Approach 2:
The patent adjusts read operation parameters dynamically based on block family characteristics and programming status. By modifying read parameters such as voltage thresholds and timing characteristics according to the specific conditions of partially programmed blocks, the system achieves higher read accuracy without requiring comprehensive system redesign.
Data Source
AI summary
A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. A read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.