Nonvolatile Memory Block Voltage Adjustment for Program Disturbance
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Solution Overview
Problem
Contemporary flash memory devices face challenges in maintaining a stable pass voltage window due to the program disturbance phenomenon, leading to disparities in threshold voltage distributions across memory cells, which affects the reliability of programming operations.
Innovation Solution
A post programming operation is implemented, where control logic adjusts the control voltage applied to word and bit lines based on the location of memory blocks within the cell array, ensuring a constant threshold voltage distribution by controlling develop time, decision level, and precharge level, thereby reducing the gap between top and bottom block threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programming operations are used without location-based voltage adjustment, then the programming process is simple and fast, but the pass voltage window becomes unstable and threshold voltage distributions vary across memory blocks
Solution Approach 1:
The patent applies local quality by adjusting control voltages based on the specific location of memory blocks within the cell array. Different memory blocks (e.g., top vs. bottom blocks) receive different control voltage levels during programming and verify operations to compensate for location-dependent threshold voltage distribution variations. This localized voltage adjustment stabilizes the pass voltage window across all memory blocks while maintaining the overall programming structure.
2Manufacturing precision
If uniform control voltage is applied to all memory blocks, then the control logic is simple, but threshold voltage distributions differ between top and bottom memory blocks
Solution Approach 1:
The control logic determines the location of each memory block and applies location-specific control voltages during programming and verify operations. This ensures that threshold voltage distributions are maintained at consistent levels across all memory blocks, eliminating disparities between top and bottom blocks while using a systematic approach to voltage adjustment.
Solution Approach 2:
The patent changes the control voltage parameter based on memory block location. By adjusting the magnitude of control voltages applied to word lines and bit lines according to the specific position of memory blocks in the array, the system achieves uniform threshold voltage distributions across different locations without requiring complete redesign of the control architecture.
3Reliability
If no post programming operation is performed, then the programming process is faster, but program disturbance causes threshold voltage distribution gaps between memory blocks
Solution Approach 1:
The patent implements a post programming operation that serves as a preliminary corrective action. After the main programming operation completes, the post programming operation adjusts threshold voltage distributions to eliminate gaps between memory blocks caused by program disturbance. This additional step ensures uniform threshold voltage levels across all blocks, improving reliability while accepting the time trade-off.
Data Source
AI summary
A nonvolatile memory device includes; a memory cell array configured into a plurality of memory blocks, a decoder connected to the plurality of memory blocks via a word line, a page buffer connected to the plurality of memory blocks via a bit line, and control logic configured to define a control voltage applied to at least one of the word line and the bit line during a program/verify operation in accordance with a location of each one of the plurality of memory blocks within the memory cell array.