Memory Block Sampling for Wear-Level Tracking in Flash Memory

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Solution Overview

Problem

Existing memory devices lack efficient methods to track the wear level of each memory block, leading to uncertainty about the device's life cycle stage and affecting the reliability and performance of program and erase operations.

Innovation Solution

Implement a memory device with a memory cell array comprising at least one first memory block and a plurality of second memory blocks, where part of the second memory blocks are selected as sampling blocks, and the peripheral circuit records erase counts only for these sampling blocks, reducing the need for extensive storage space and enabling precise tracking of the device's life cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If erase counts of all memory blocks are recorded, then wear level tracking is complete, but storage space requirement increases significantly

Engineering Contradiction:
Improvewear level tracking accuracyVSAvoidstorage space
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent extracts only the necessary wear level information by recording erase counts only for sampling blocks rather than all memory blocks. This selective extraction maintains sufficient wear tracking accuracy while significantly reducing storage space requirements in the first memory block.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses sampling blocks as representative copies of the entire memory block population. By recording wear levels of these sampling blocks, the system obtains representative data that reflects the overall wear state without needing to store complete wear information for every single memory block.

Inventive Principle:
Principle #26Copying

2Quantity of substance

If sampling blocks are used to track wear levels, then storage space is reduced, but wear tracking completeness may be compromised

Engineering Contradiction:
Improvestorage spaceVSAvoidwear level tracking accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent applies local quality by treating sampling blocks differently from non-sampling blocks. Sampling blocks are selected specifically for wear tracking purposes, while non-sampling blocks operate normally without dedicated wear recording. This differentiation optimizes the balance between tracking accuracy and storage efficiency.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses partial action by recording wear information only for a subset (sampling blocks) of memory blocks rather than all blocks. This partial recording approach provides sufficient wear level information for reliability assessment while avoiding the excessive storage cost of complete recording across all memory blocks.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If extensive storage space is allocated for wear tracking, then complete wear monitoring is achieved, but device complexity increases

Engineering Contradiction:
Improveoperation reliabilityVSAvoidstorage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts only the essential wear tracking functionality from the complete memory block management system. By isolating wear recording to sampling blocks and using the first memory block exclusively for wear data, the system achieves reliable wear monitoring with simplified storage structure and reduced complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250348423A1Memory devices, operation methods thereof, and memory systems
Publication Date: 2025.11.13 YANGTZE MEMORY TECH CO LTD
  • US20250348423A1 patent drawing
  • US20250348423A1 patent drawing
  • US20250348423A1 patent drawing

AI summary

Examples of the present disclosure disclose a memory device and an operation method thereof and a memory system. The memory device comprises a memory cell array and a peripheral circuit coupled with the memory cell array. The memory cell array includes at least one first memory block and a plurality of second memory blocks, and part of the plurality of second memory blocks are configured as sampling memory blocks; and the peripheral circuit is configured to: perform an erase operation on the sampling memory block; and record an erase count of the sampling memory block in the first memory block.