Semiconductor Memory Block Word Line Erase Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving efficient erase operations, particularly in terms of speed, due to limitations in voltage application and word line management across memory blocks.
Innovation Solution
The semiconductor memory device employs a method where at least two memory blocks share a block word line, with specific voltage applications to the block word line and global word line to facilitate faster erase operations by ensuring pass transistors are turned on and local word lines are floated, allowing for efficient data erasure regardless of threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple memory blocks share one block word line, then device complexity is reduced, but erase speed deteriorates due to voltage distribution issues
Solution Approach 1:
The patent segments the word line control into multiple independent components: block word line (BWL) for block selection, global word line (GWL) for unselected block control, and local word line (LWL) for individual memory block control. This segmentation allows each word line to be optimized independently for its specific function, resolving the contradiction between shared structure benefits and erase speed requirements.
Solution Approach 2:
The patent applies different voltage levels to different word lines based on their specific functions: BWL receives first voltage to turn on pass transistors, GWL receives second voltage to float local word lines in unselected blocks, and LWL receives third voltage during erase operations. This local quality differentiation ensures optimal voltage distribution for both shared and individual block operations, maintaining high erase speed while using shared word line structures.
2Reliability
If high voltage is applied to block word line to turn on pass transistor, then erase operation reliability is improved, but voltage transfer to memory cells deteriorates
Solution Approach 1:
The patent applies voltage to the block word line in a preliminary action before the actual erase operation to turn on pass transistors and establish proper conduction paths. This preliminary voltage application ensures that when the erase voltage is subsequently applied to the local word line, the voltage can be efficiently transferred to memory cells without loss, resolving the contradiction between reliability and voltage transfer efficiency.
Solution Approach 2:
The pass transistor acts as an intermediary element between the block word line and the memory cells. By controlling the pass transistor's on-state through block word line voltage, the patent ensures efficient voltage transfer from the local word line to the memory cells during erase operations, maintaining both reliability and voltage transfer efficiency.
3Reliability
If erase voltage is applied to source line, then erase operation effectiveness is improved, but bit line precharging deteriorates for high threshold voltage cells
Solution Approach 1:
The patent dynamically adjusts the voltage levels of different word lines during the erase operation. The block word line voltage is adjusted to control pass transistor conduction, while the local word line voltage is dynamically set to float during erase to enable effective voltage transfer. This dynamic voltage control ensures both effective erase operation and proper bit line precharging even for high threshold voltage cells.
Data Source
AI summary
The present disclosure relate a method of operating a semiconductor memory device including at least two memory blocks sharing one block word line. The method including applying an erase voltage to a source line commonly coupled to the memory blocks, one of which is a selected memory block and applying a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when the erase voltage is applied to the source line, wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.