Non-volatile Memory Blocking Insulation with Sub-layers
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Solution Overview
Problem
Conventional non-volatile memory devices face issues with increased parasitic capacitance and leakage current due to reduced intervals between floating gates, leading to interference between adjacent memory cells and decreased erase operation speed, especially when using high-k dielectric layers as blocking insulation.
Innovation Solution
The introduction of an interface layer pattern with different materials from the blocking insulation pattern, which reduces leakage current and parasitic capacitance by improving the interface junction characteristics between the charge storage and control gate electrodes, and the use of a multi-layered blocking insulation structure with varying energy band gaps to control back tunneling currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the interval between floating gates is decreased to increase integration density, then device integration is improved, but parasitic capacitance increases causing interference between adjacent memory cells
Solution Approach 1:
The blocking insulation pattern is divided into multiple sub-layers (first, second, third sub-layers) with different energy band gaps. This segmentation allows each sub-layer to perform specific functions: the first and third sub-layers with lower band gaps control charge transfer, while the second sub-layer with higher band gap reduces parasitic capacitance and prevents interference between adjacent memory cells.
Solution Approach 2:
Different sub-layers of the blocking insulation pattern are assigned different energy band gap properties. The first and third sub-layers have lower energy band gaps optimized for charge transfer, while the second sub-layer has a higher energy band gap specifically to reduce parasitic capacitance in the high-density configuration. This local differentiation of material properties resolves the contradiction between integration density and parasitic capacitance.
2Reliability
If a high-k dielectric layer is used as blocking insulation to increase coupling ratio, then coupling efficiency is improved, but leakage current increases between charge storage pattern and control gate electrode
Solution Approach 1:
The blocking insulation pattern is constructed as a composite structure with multiple sub-layers having different energy band gaps. This composite material approach allows the first and third sub-layers (with lower band gaps) to provide good coupling ratio, while the second sub-layer (with higher band gap) suppresses leakage current. The combination of materials with different properties resolves the contradiction between coupling efficiency and leakage current.
Solution Approach 2:
The energy band gap parameter is varied across different sub-layers of the blocking insulation pattern. By changing the energy band gap from lower (in first and third sub-layers) to higher (in second sub-layer), the structure achieves both high coupling ratio and low leakage current, resolving the contradiction through parameter optimization.
3Reliability
If the height of floating gate is increased to augment coupling ratio, then coupling efficiency is improved, but conductive layer for control gate electrode cannot be completely filled between floating gates
Solution Approach 1:
Instead of increasing floating gate height in the vertical dimension, the solution introduces a multi-layered blocking insulation structure with different energy band gaps. This dimensional approach to solving the coupling ratio problem avoids the manufacturing difficulty of filling conductive layers in high-aspect-ratio structures, while still achieving improved coupling efficiency.
4Quantity of substance
If interval between floating gates is reduced, then integration density is improved, but interference phenomenon between adjacent memory cells increases
Solution Approach 1:
The blocking insulation pattern is segmented into multiple sub-layers with different energy band gaps. The second sub-layer with higher energy band gap specifically addresses the interference problem between adjacent memory cells by reducing parasitic capacitance, while allowing the overall structure to maintain high integration density through reduced floating gate intervals.
Solution Approach 2:
The second sub-layer of the blocking insulation pattern is specifically designed with higher energy band gap properties to locally address the interference issue between adjacent memory cells. This local quality differentiation allows the structure to maintain high integration density while preventing interference in critical regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage current and parasitic capacitance, enhances retention time, and improves the operating speed of erase operations in non-volatile memory devices by effectively managing charge transfer and energy band gaps.
Implementation Method 1
the blocking insulation pattern may include a first blocking insulation sub-layer, a second blocking insulation sub-layer, and a third blocking insulation sub-layer... an energy band gap of the second blocking insulation may be greater than energy band gaps of the first and third blocking insulation sub-layers
Data Source
AI summary
A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.