Memory Device Body Contact Leakage Reduction
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Solution Overview
Problem
The OFF-state leakage current in transistors with floating body cells is high due to parasitic bipolar junction transistor operation, which affects device performance.
Innovation Solution
A memory device design that includes a body contact below the source of the transistor, which introduces accumulated holes out of the transistor body, reducing OFF-state leakage current. The manufacturing method involves forming a capacitor, a body contact, and a transistor with specific implantation processes to achieve this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a floating body cell structure is used in the transistor, then the transistor can store carriers through impact ionization, but the OFF-state leakage current becomes considerably high due to parasitic BJT operation
Solution Approach 1:
The invention extracts the harmful accumulated holes from the floating body by introducing a dedicated body contact that provides a separate extraction path. The body contact is positioned to receive holes directly from the body region, removing them before they can trigger parasitic BJT operation and cause leakage current.
Solution Approach 2:
The body contact acts as an intermediary element between the floating body and the substrate. It provides a controlled interface for hole extraction, mediating the interaction between the stored carriers and the substrate to prevent harmful parasitic effects while maintaining the floating body's storage function.
2Area of stationary object
If the drain is positioned over the capacitor, then the device area is reduced, but the manufacturing precision required for aligning the drain with the capacitor increases
Solution Approach 1:
The capacitor is formed first in the substrate, establishing a fixed reference structure before the transistor components are added. This preliminary formation of the capacitor provides a stable foundation that simplifies subsequent alignment operations, as the capacitor's position and dimensions are already determined.
Solution Approach 2:
The drain is positioned to overlap with the capacitor in the vertical direction, creating a nested arrangement where the drain sits over the capacitor structure. This nesting reduces the horizontal footprint of the device while the vertical stacking accommodates the alignment requirements through the layered structure.
3Object-generated harmful factors
If the source is vertically spaced apart from the body contact, then the parasitic BJT operation is reduced, but the transistor channel length control becomes more difficult
Solution Approach 1:
The body contact is positioned at a specific location below the source, creating a localized hole extraction region. This local quality ensures that hole extraction occurs primarily at the body contact interface rather than throughout the entire source-body interface, reducing parasitic BJT operation while maintaining controlled channel characteristics through the specific geometry of the source-body contact arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of the body contact effectively reduces the OFF-state leakage current, improving the overall performance of the memory device by managing the transient storage of holes.
Implementation Method 1
The body contact vertically below the bit line contacts... introduces the accumulated holes out of the body of the transistor
Implementation Method 2
performing a first implantation process to form a drain of the transistor... performing a second implantation process to form the source of the transistor
Data Source
AI summary
A memory device includes a substrate, a capacitor, a transistor, a word line, a bit line contact and a body contact. The capacitor is over the substrate. The transistor is over the capacitor, and the transistor includes a channel region, a gate over the channel region, and a source and a drain on opposite sides of the channel region, in which the drain is over the capacitor. The word line is over and electrically connected to the gate of the transistor. The bit line contact is over and electrically connected to the source of the transistor. The body contact is below the source of the transistor.