3D Memory Chiplet Bond Pad Layout for Misalignment-Tolerant Bonding

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Solution Overview

Problem

The challenge of efficiently connecting control circuits in a control die with corresponding memory die components is exacerbated by size mismatches and misalignment issues in die-to-wafer bonding, making direct connection challenging and requiring bond pad arrangements that are tolerant of misalignment.

Innovation Solution

Distribute word line bond pads over a wide area, including locations in the array area over bit lines and memory cells, with traces extending into the memory array area, and arrange bond pads in a repeated hexagonal pattern to accommodate misalignment, while using traces to connect vias that are interleaved between directly connected and indirectly connected vias.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bond pads are arranged for direct connection in die-to-wafer bonding, then connection efficiency is improved, but misalignment and size mismatch issues worsen

Engineering Contradiction:
Improveconnection efficiencyVSAvoidalignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The bond pad arrangement is segmented into multiple zones: directly connected bond pads for precise alignments and indirectly connected bond pads (via traces extending into the memory array area) for misaligned connections. This segmentation allows the system to handle both direct and indirect connections within the same die-to-wafer bonding process, resolving the contradiction between connection efficiency and alignment precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the parameter of bond pad connectivity from binary (directly connected or not) to a spectrum including directly connected, indirectly connected via traces, and optionally connected. By introducing trace-based indirect connections with varying extension lengths into the memory array area, the system can adapt to different alignment scenarios while maintaining connection functionality.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If bond pads are distributed over a wide area including array area, then misalignment tolerance is improved, but device complexity increases

Engineering Contradiction:
Improvemisalignment toleranceVSAvoidbond pad arrangement complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory array area serves multiple functions: it stores data and also provides space for extending traces to create indirectly connected bond pads. This multi-functionality allows the bond pad arrangement to tolerate misalignment without requiring dedicated compensation structures, as the existing array area is reused for alignment compensation purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention creates a repeated hexagonal pattern of bond pads distributed across the die surface, including the array area. This periodic replication of the bond pad pattern provides multiple potential connection points that can accommodate misalignment through the hexagonal geometry's inherent tolerance properties.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20250323195A1Memory chiplet bond pad configuration
Publication Date: 2025.10.16 SANDISK TECHNOLOGIES LLC
  • US20250323195A1 patent drawing
  • US20250323195A1 patent drawing
  • US20250323195A1 patent drawing

AI summary

An apparatus includes a memory die having a 3D memory structure that includes nonvolatile memory cells in an array area. The nonvolatile memory cells are connected by word lines and bit lines. The word lines are connected to vertical word line vias in a staircase area adjacent to the array area. The vertical word line vias include a first plurality of vertical word line vias connected to first word line bond pads in the staircase area and a second plurality of vertical word line vias connected to second word line bond pads in the array area.