Cell-Over-Periphery Memory Bonding Alignment Compensation
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Solution Overview
Problem
Existing memory devices face challenges in reducing size while maintaining performance, detecting defects easily, and preventing performance degradation.
Innovation Solution
A memory device structure comprising a first semiconductor layer with a memory cell array and bonding/test pads, and a second semiconductor layer with a peripheral circuit and additional bonding/test pads, where a test circuit checks the connection state of the bonding pads and compensates the peripheral circuit operation based on test result signals, allowing for adjustment of sensing time and operating voltage to address misalignments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If elements are fabricated on separate wafers and bonded together, then integration degree increases and size reduces, but misalignment between bonding pads occurs and performance degrades
Solution Approach 1:
The patent applies preliminary action by forming test pads and bonding pads with predetermined patterns on separate wafers before bonding. The test pads are specifically designed to detect alignment status after bonding, allowing the system to identify and compensate for misalignment issues before final device operation. This preliminary preparation enables subsequent correction of alignment errors that would otherwise degrade device performance.
Solution Approach 2:
The patent implements feedback through test circuits that receive test signals from test pads and generate test result signals indicating alignment status. These feedback signals are used to determine whether misalignment has occurred and to control whether to operate normally or in a compensated mode. The peripheral circuit adjusts its operation based on the test results, providing real-time feedback-driven adaptation to alignment variations.
2Ease of manufacture
If bonding pads are used to connect separate wafers, then device integration is achieved, but defect detection becomes difficult
Solution Approach 1:
The patent introduces test pads as intermediary elements between the bonding pads and the test circuits. These test pads serve as dedicated mediators for detecting alignment issues without interfering with the normal bonding function. The test circuits connect to these intermediary test pads rather than directly to bonding pads, enabling separate defect detection pathways that do not compromise the primary bonding function.
Solution Approach 2:
The patent segments the bonding pad function into two distinct components: bonding pads for electrical connection and test pads for alignment detection. This segmentation allows the testing function to be separated from the bonding function, enabling independent optimization of each. The test pads can be specifically designed for detection purposes while bonding pads maintain their bonding functionality, making defect detection easier without compromising integration.
3Reliability
If misalignment between bonding pads occurs, then device performance degrades, but compensation mechanisms increase device complexity
Solution Approach 1:
The patent applies partial action by providing compensation only when misalignment is detected through test signals. The system does not continuously operate in compensated mode but rather adapts its operation based on actual alignment status. The test circuits determine whether to operate normally or in a compensated mode, applying compensation only to the extent necessary to correct detected misalignment issues, thereby avoiding unnecessary complexity.
Solution Approach 2:
The system performs self-diagnosis and self-compensation through integrated test circuits that automatically detect misalignment and adjust operation accordingly. The peripheral circuit controls the memory cell array and automatically adjusts its operation based on test result signals, eliminating the need for external alignment verification or manual compensation. The device essentially tests and compensates for its own alignment issues, reducing overall system complexity.
Data Source
AI summary
An example memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bonding pad, and a first test pad. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit, a second bonding pad connected to the first bonding pad, a second test pad connected to the first test pad, and a test circuit. The test circuit checks a connection state of the first and second bonding pads. The test circuit receives a first test signal through the first and second test pads, generates a first test result signal representing a first misalignment between the first and second bonding pads based on the first test signal, and compensates an operation of the peripheral circuit based on the first test result signal.