Multi-Chip Memory Bonding With Protected Alignment Marks

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory device technologies face challenges in efficiently manufacturing and integrating magnetic memory devices with precise alignment and high accuracy, particularly in the bonding process of chips, which affects the reliability and yield of the manufacturing process.

Innovation Solution

The proposed solution involves a method for manufacturing magnetic memory devices where two chips are bonded together, utilizing anodic oxidation to form alumina holes with regular and irregular alignment areas, allowing for precise alignment marks and improved alignment accuracy during the lithography process, and using these marks to ensure accurate placement of components like switching elements and reading elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional chip bonding methods are used, then manufacturing process is simpler, but alignment accuracy deteriorates

Engineering Contradiction:
Improvealignment accuracyVSAvoidbonding process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Alignment marks are formed on the chips before the bonding process. These pre-formed marks serve as reference points that guide the bonding alignment, ensuring high precision without requiring complex real-time adjustment mechanisms during the bonding operation itself.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The alignment marks act as intermediary reference elements between the two chips being bonded. By providing visible, pre-defined positional references on both chip surfaces, the marks mediate the alignment process, allowing operators or automated systems to achieve precise positioning without complex measurement equipment.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If alignment marks are not protected, then manufacturing process is simpler, but alignment mark accuracy deteriorates due to deformation

Engineering Contradiction:
Improvealignment mark accuracyVSAvoidprocess simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The alignment marks are formed and positioned on the chips before the bonding and subsequent processing steps. This preliminary formation ensures that the marks are established at their correct positions before any deformation-prone operations occur, protecting their accuracy throughout the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The alignment marks are designed and positioned to withstand subsequent processing steps. By anticipating potential deformation from bonding heat or mechanical stress, the mark design and placement are optimized to maintain accuracy despite these unavoidable process conditions.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the manufacturing process reliability and yield by maintaining alignment mark accuracy and preventing deformation during anodic oxidation, resulting in improved alignment and reduced substrate handling issues, even with large-diameter wafers.

Implementation Method 1

utilizing anodic oxidation to form alumina holes with regular and irregular alignment areas

Methodology Applied
Scientific EffectAnodic oxidation: Anodising

Data Source

PatentUS11942466B2Memory device having multiple chips and method for manufacturing the same
Publication Date: 2024.03.26 KIOXIA CORP
  • US11942466B2 patent drawing
  • US11942466B2 patent drawing
  • US11942466B2 patent drawing

AI summary

According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.